[PCB_FORUM] Re: linewidth change
- From: "David Greig" <David@xxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 9 Sep 2004 17:47:15 +0100
Is the environment variable acon_no_impedance width unset? This would let
the tool adjust line width to compensaye for impedances on each layer.
I set it because I don't agree with the Allegro methodology for calculating
impedance. Correct impedance calculations are easy enough to do (or you can
resort to Method Of Moments 2D tools) Either will give more satisfactory
results.
Another reason for not letting the tool decide is if you want to identify
controlled impedance routes by layer to the fab shop. Just make sure that
your plane fill aperture is different from the controlled line width or the
fab shop will have a harder time of it!
Best Regards
David Greig
_________________________________________
Director
GigaDyne Ltd
Buchan House
Carnegie Campus
Dunfermline KY11 8PL
United Kingdom
Tel. +44 (0) 1383 62 49 75
_________________________________________
_____
From: westfeldt [mailto:westfeldt_nbcd@xxxxxxxxx]
Sent: 09 September 2004 16:27
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] linewidth change
Still getting used to v15.1. Sometimes tracewidth goes from my current
width to minimum drc value when I drop a via; didn't do that in my v14.2.
How do I fix this?
Patrick Westfeldt, Jr.
North Boulder Circuit Design
westfeldt_nbcd@xxxxxxxxx
720-406-0887
c 720-272-5822
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