After Component Placement and Autoswap-Gates/Pins using the Virtual wirelength reduction algorithym I am still left with many crosses in my rats which could be removed, but because they do not reduce the overall length they do not get swapped, however, removing the crosses would be preferreable as a solution for this design as I think it would be for many. I have spent much time with the placement, customized the fanout to optimize routing and help eliminate crosses but I am still looking at spending more time manually swapping gates to eliminate hourglasses. This is critical as these runs can not use vias other than fanout and their length must be as short as possible. I would like to get it done right the first time as we are not closely coupled with the Front end tool and the backannotation process unfortunately is not 'pushbutton' and I would like to reduce cycles in that area as well. Is anyone aware of a function that could speed this 'swap/rats crosses' process up? Any help would be appreciated. Thank You. -Lcan Rekahs