[PCB_FORUM] SI Problem !!!
- From: "Naren" <naren@xxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 17 Mar 2005 09:36:22 +0530 (IST)
Hi All !
I have circuit in which Test chip is mounted on Test Socket;
It's o/p is going to LVDS Driver.
My problem is i don't have IBIS/Spice models for Testchip & Socket.
But I have RLC (Parasitics) Metrix for both.
can I simulate the signal with above parameters in Allegro Spectaquest
15.2?
--
"Keep looking foreward"
Regards
Naren Thesia
Member CAD
D'GIPRO SYSTEMS PVT. LTD. BANGALORE
TEL: 080-25219017/18 (O)
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