[PCB_FORUM] Oddball FET Footprint
- From: "Ritter, Alan" <Alan.Ritter@xxxxxxxxxx>
- To: "icu-pcb-forum@xxxxxxxxxxxxx" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 25 Jun 2012 12:14:10 -0400
I'm working on the PCB footprint for a Siliconix (Vishay) Si7308DN FET.
Nominally, it's an 8-pin part, but the thermal pad partially overlays pins 5-8
(the drain connections to the FET). The recommended layout has the 8
individual pins plus the thermal pad. Obviously, adding this as a ninth pad or
a filled shape creates DRCs with pins 5-8.
Anyone have any bright ideas for how to lay this beast out to avoid DRCs and
keep with the recommended pad configuration for the part?
Alan Ritter
Surgical Equipment Design & Development
Engineering Fellow
(636) 226-3364 (Office)
(636) 226-3552 (FAX)
(314) 488-1139 (Mobile)
Bausch + Lomb
3365 Treecourt Ind. Blvd.
St. Louis, MO 63122
www.bausch.com<http://www.bausch.com/>
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