[PCB_FORUM] Re: Logo on Top Etch layer
- From: "Jonathan Friedman" <jf@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 29 May 2006 21:00:37 -0700
>> "Etching layer gives more detail, and because of that the logo can be
smaller."
> .....HOW????
...because the silk-screen process at virtually every fab shop is not as
high-resolution as the metal etching process. Part of this is just the
machinery (why build a really expensive silk-screen when it sits inside the
product enclosure unseen most of its life?) and part of this is the physics
of the process itself. Etching is a negative process (remove the unwanted
material), silk is a positive process (add the wanted material). The ink
bleeds when deposited providing a fundamental limit on the resolution
attainable for lines and curves. There are some electro-magnetic reasons for
not putting the logo in the metal (floating metal poses ESD risk and
detuning of nearby trace impedances) or on the silk (silk over the metal
trace will lower the effective dielectric constant), but all of that is
application specific. There is fundamentally no reason, with careful design,
why you couldn't/shouldn't put the logo in the metal (or in the silk). You
could even remove the soldermask over it to make it look all shiny... Wow!
;-)
Cheers!
-Jonathan
Jonathan Friedman, GSR
Networked Embedded Systems Laboratory (NESL)
University of California, Los Angeles (UCLA)
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