All,
I think that if you wanted to have different phase values in the ECSet,
you would most likely name a new class and assign the new rule and set
the value there. Is that correct?
Andrew
-----Original Message-----
From: Gerry Meier [mailto:gerry.meier@xxxxxxxxxxxxxx]
Sent: Thursday, March 10, 2005 2:53 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Diff pair Constraints and CM
Dave,
You can still set your phase tolerance, etc in CM if you are using the
NET_PHYSICAL_TYPE.
Just do not put any values (blank) in the items you are setting in the
NET_PHYSICAL_TYPE.
Regards,
Gerry
Gerry Meier
Sr. PCB Designer
Freedom CAD Services, Inc.
Voice: (603) 864-1300 x1350
Alt. Voice: (386) 753-0048
Email: gerry.meier@xxxxxxxxxxxxxx
visit our website at<http://www.freedomcad.com
-----Original Message-----
From: Dave Seymour [mailto:deseymour-pcb@xxxxxxxxxxxxx]
Sent: Thursday, March 10, 2005 5:30 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Diff pair Constraints and CM
Kevin,
No confusion taken. To me this is important to understand the different
ways the tools works. Each must find their own path.
Having said, Allow me to summerize:
Please read this over and tell me if I'm wrong or left out something.
I come up with 3 mode of operation.
Not understanding yet, that if two modes are used and set. Which one
overrides.
Thanks
dave
Mode #1: NET_PHYSICAL_TYPE
PRO:
If layer control is important, different line widths different layers.
Then the only place to set this up is in the NET_PHYSICAL_TYPE forms.
CON:
I don't see anyway to set up length control, ie. the net+ and net- can
be way different in length.
Mode #2 electrical_constraints
PRO:
If all diff pairs can be the same then one can set
constraints>electrical_constraints. Getting length control, Couple Tol,
and Gather, etc. This can become a "CSET_NAME" that can be applied with
the edit property ELECTRICAL_CONSTRAINT_SET = CSET_NAME.
Basicly, the same as the CM, but not using the CM.
CON:
Line widths won't be different for different layers.
Mode #3 CM
PRO: CM gives one all the parameters and one can copy and apply an the
CSET_NAME from above in spreadsheet format.
CON:
The same "Line widths won't be different for different layers."
-----Original Message-----
From: Kevin McCowan <kmccowan@xxxxxxxxxxxxxx>
Sent: Mar 10, 2005 2:12 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Diff pair Constraints and CM
Well, I guess I opened a can of worms, didn't I?
What I have done to circumvent this issue is to get a stackup that has
the same width and space for all internal layers and not allow the pairs
on the outside of the board where it is difficult to get them the same.
I agree with everyone (and it seems like it was everyone!) as to how to
do them with different rules on different layers. I just found my way to
allow me to use the diff pair constraints.
Sorry for any confusion.
Kevin
Austin Franklin wrote:
Hi Andrew,
This is not necessarily true for diff pair stuff, when you have
different widths and spacing for different layers. For instance, outer
layers tend to have different spacing characteristics than inner
layers (not always.. but for the point of illustration).
I just did things this way...
In this case, you would NOT enter the values in the Electrical
constraints/Diff pair area, but back in Physical constraints, where
we're all used to doing it. The important thing here is that you would
simply leave those entries blank in the Electrical constraints/Diff
pair setup.
Ah, this I did not do. I'll review what I did based on this, thanks!
Which takes precedence? If I enter it in the EC/DP set-up, and I have
an outer layer value set different in PC, which value will it use for
the outer layers?
Regards,
Austin
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