Hi, Any body having Experience in Conversion from Cam350 to powerpcb and powerpcb to allegro I have Tried by following steps. Cam 350 1.imported Gerber's and build a part also I have extracted the net list. 2.Exported the gerber as .ASC format in powerpcb ver2.0 Powerpcb 1.Imported the .ASC file in to Powerpcb 2.Again I have exported as .ASC format. Allegro 1.Imported .asc file(which i have exported from pads) in to allegro by using file /Import/PADS/ option. The time of conversion allegro shows error and it closing.(pls find attached the viewlog file) I opened the board file which is created in allegro, I am missing the Traces. Components are coming. line,Board outline is coming in allegro. But traces are not coming in to allegro. Doubts 1.Why the traces are not importing in to allegro 2.Also Allegro is not taking directly the .ASC exported from CAM350.Allegro is accepting only the .asc file which exported only from powerpcb. Why ? 3.Pls Explain the step by step flow for this conversion. Thanks in advance. Regards K.Vivek Pcb Designer, Hcl Technologies, Chennai, India. <<vielogerr.txt>> DISCLAIMER This message and any attachment(s) contained here are information that is confidential, proprietary to HCL Technologies and its customers. Contents may be privileged or otherwise protected by law. The information is solely intended for the individual or the entity it is addressed to. If you are not the intended recipient of this message, you are not authorized to read, forward, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer
Translating D:\jobs\test\s1682_apr25vivek5.asc. Reading PADS ASCII file header. Version = PowerPCB2.1 Route Layers = 4 Units = MILS Hatch mode = Vertical / Horizontal Hatch grid = 2.000000, angle = 0.000000, anti-pad spacing = 25.000000 Initializing new database. Creating layers. Reading PADS ASCII file body. *PARTTYPE* *MISC* *MISC* *MISC* *MISC* *MISC* *TEXT* *LINES* *VIA* *PARTDECAL* *PARTTYPE* *PART* *ROUTE* Writing routes. *END* =============================================================================== PADS layer usage summary: Layers 1 to 4 are route layers. LINES: 1 ETCH - TOP 2 ETCH - INTERNAL1 3 ETCH - INTERNAL2 4 ETCH - BOTTOM 6 * Not mapped! 7 * Not mapped! 10 * Not mapped! COPPER: TEXT: 8 * Not mapped! 10 * Not mapped! DECALS: PADS: 0 ETCH - internal_pad_def 1 ETCH - TOP 2 ETCH - INTERNAL1 3 ETCH - INTERNAL2 4 ETCH - BOTTOM 6 * Not mapped! 7 * Not mapped! 9 * Not mapped! 10 * Not mapped! VIAS: 0 VIA CLASS - internal_pad_def 1 VIA CLASS - TOP 2 VIA CLASS - INTERNAL1 3 VIA CLASS - INTERNAL2 4 VIA CLASS - BOTTOM 6 * Not mapped! 7 * Not mapped! 9 * Not mapped! WARNING: 582 data objects mapped to the UNUSED class were ignored. =============================================================================== Creating D:\jobs\test\s1682_apr25vivek5.brd. Loading netlist: D:\jobs\test\s1682_apr25vivek5.TXT Writing database. ERROR: Error while writing the Allegro database. Closing database. Translation complete. Finished with errors!