[ibis-quality] Minutes from the 14 Aug 2007 ibis-quality meeting

From: "Mike LaBonte \(milabont\)" <milabont@xxxxxxxxx>
To: <ibis-quality@xxxxxxxxxxxxx>
Date: Mon, 20 Aug 2007 16:30:08 -0400

Minutes from the 14 Aug 2007 ibis-quality meeting are attached. ARs:

AR: David rewrite IQ 5.2.2 as a level 2 check

Mike

Minutes, IBIS Quality Committee

14 Aug 2007

11-12 AM EST (8-9 AM PST)

ROLL CALL
  Adam Tambone
  Barry Katz, SiSoft
  Benny Lazer
  Benjamin P Silva
  Bob Cox, Micron
* Bob Ross, Teraspeed Consulting Group
  Brian Arsenault
* David Banas, Xilinx
  Eckhard Lenski, Siemens
  Eric Brock
  Gregory R Edlund
  Hazem Hegazy
  John Figueroa
  John Angulo, Mentor Graphics
  Katja Koller, Siemens
  Kevin Fisher
  Kim Helliwell, LSI Logic
  Lance Wang, IOMethodology
  Lynne Green
* Mike LaBonte, Cisco
  Mike Mayer, SiSoft
* Moshiul Haque, Micron Technology
  Peter LaFlamme
  Radovan Vuletic, Qimonda
  Robert Haller, Enterasys
* Roy Leventhal, Leventhal Design & Communications
  Sherif Hammad, Mentor Graphics
  Todd Westerhoff, SiSoft
  Tom Dagostino, Teraspeed Consulting Group
  Kazuyoshi Shoji, Hitachi
  Sadahiro Nonoyama

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for patent for disclosure:

- No one declared a patent.

AR Review:

- Mike email new 5.2.2 text to Roy
  - Done

- Roy write a sentence to describe the population scope of 5.2.8
  - Done

New items:

5.2.2.  {LEVEL 3}  [Model] Vinl and Vinh reasonable
- Moshiul: Sometimes AC values are used for Vinl/Vinh
- David:
  - IC makers use JEDEC spec numbers for Vinl/Vinh.
  - Parts are tested to make sure the actual is well within specs.
  - The numbers are usually easy to meet.
- Bob: We can't get true Vinl/Vinh values
  - It is a percentage of VDD anyway
- Mike: The IBIS spec doesn't describe Vinh/Vinl well
  - The only mention of "DC" is in the example
    Vinl = 0.8V | Input logic "low" DC voltage, if any
    Vinh = 2.0V | Input logic "high" DC voltage, if any
  - Roy: We can't determine this for a single buffer
  - David: Presumably they are worst case numbers
- Mike: Vinl/Vinh as described aren't really useful for timing
  - Maybe this should not be a level 3 check
  - Should we write a BIRD to have the definition improved?
- Bob: [Receiver Thresholds] can be used to describe timing thresholds
  - This is not the current recommendation for non-DDR parts
  - We are stuck with Vinl/Vinh as defined in IBIS
- Roy: Vinl/Vinh are fine for 1st switch/final settle on slow technologies
- Mike: This check should discuss [Receiver Thresholds], etc.
  - [Model Spec] & [Receiver Thresholds] override [Model] 
- David: A truly good level 3 model would have [Receiver Thresholds]
- David: The waveform has to go above AC to switch, then has to remain above DC
- Moshiul: Sometimes AC is used, sometimes DC
  - It depends on what data are available
- Roy: This may be a topic for the IBIS committee
- Bob: IBIS should not specify how the data is used
  - It is up to the EDA tool to provide useful capabilities
- We could make this a level 2 check and simplify the description

AR: David rewrite IQ 5.2.2 as a level 2 check

Next meeting:

21 Aug 2007
11-12 AM EST (8-9 AM PST)
Phone: 1.877.384.0543 or 1.800.743.7560
Passcode: 90437837

Meeting ended at 12:07 PM Eastern Time.

[ibis-quality] Minutes from the 14 Aug 2007 ibis-quality meeting

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