[ibis-macro] Flow
- From: "Mellitz, Richard" <richard.mellitz@xxxxxxxxx>
- To: "ibis-macro@xxxxxxxxxxxxx" <ibis-macro@xxxxxxxxxxxxx>
- Date: Tue, 20 Oct 2009 15:30:10 -0600
I'm trying wrap my mind around the concept of flow that y'all are tossing
about. Maybe an interface spec is more pertinent? What is the role and
responsibility of each feature? What are the pipes between? Adaptive
equalization may require a number different flow steps depending on operation.
Let's take PCIe Gen3 as an example. I think at very minimum IBIS-AMI should
support that. It's not too different from IEEE802.3ap.
There is a notion of downstream (motherboard) and upstream. The Rx is in
control but the downstream device lends hints to start (per spec).
First the downstream device commands the upstream device as to where Tx eq tap
setting should start.
The Rx can either take those hints or tell the Tx go an initialization
equalization pre-set. The Rx could decide it doesn't want any Tx Eq and do FFE
in the Rx unannounced to anybody.
Now training may occur if the Rx wants adjust the Tx per spec. A special
pattern is used. The Rx may recursively tell the Tx to change taps. In all
likelihood it would not be a zero forcing solution for taps because of some Rx
linear EQ. It may use the Tx tap adjustment as an AGC.
Once the Tx taps are locked in training, the Rx can accept transmitted data
through the channel and do its EQ operation which will in all likelihood be non
LTI.
One flow could use the bit stream convolution or PDA for the above and just
determine the equalization setting internal to the Rx and Tx. Subsequently a
data edge PDF convolution could be used to create a CDF BER eye. (I think you
are calling this statistically simulation) Some folks are looking for 1e-14 BER
or better an want to analyze a CDF BER eye.
How would IBIS-AMI handle this scenario?
Thanks,
... Rich Mellitz, Intel
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