[hsdd] High-Speed Digital Design Newsletter - Big Buffer
- From: "Dr. Howard Johnson" <howie03@xxxxxxxxxx>
- To: <hsdd@xxxxxxxxxxxxx>
- Date: Fri, 28 Oct 2005 14:22:58 -0700
BIG BUFFER
HIGH-SPEED DIGITAL DESIGN - online newsletter -
Vol. 8 Issue 07
My latest movie "Power Integrity Basics" is now complete, and
will be aired on the web for the first time November 9, 2005.
This movie explores the distributed nature of power and ground
planes in your pcb. In the film I demonstrate the correct
method for defining and measuring voltages within a
distributed system, discuss the placement and modeling of
bypass capacitors, and show some cool animations of the
distributed behavior of the actual power system on an Intel
processor card. Thanks to Sigrity, Intel and Tektronix for
their help making this production possible.
For registration, see http://webcast.you-niversity.com/sigrity.
My business office is planning a seminar next Spring, possibly
in the Raleigh N.C. region. If you know a good conference
hotel in that area suitable for classes of up to 90 people,
please drop a line to: jennifer@xxxxxxxxxx
______________________________________________________
BIG BUFFER
Ed Hitt of Louisville, Colorado writes [edited for clarity]:
What is the purpose of using a buffer-driver (EG 74LCX125) to
drive a circuit with a large capacitive load?
Is it merely to make the rise time faster by decreasing the
output impedance of the driving circuit, thereby increasing
the timing margin, or is the low current drive capability of
the non-buffer gate simply not adequate?
Is there any reason to think that the large current due to C
dv/dt might damage a non-buffer type gate?
______________________________________________________
Dr. Johnson replies:
The output impedance and the current-driving capability of a
driver are intimately related. Comparing two totem-pole CMOS
drivers operated at the same power-supply voltage, a larger
current-driving capability almost always implies a smaller
output resistance.
Figure 1 illustrates the complete form of the output voltage-
current relationship for a typical CMOS totem-pole driver.
This type of plot is called a V-I diagram (or sometimes an I-V
diagram). The vertical axis represents current emanating from
your driver. The horizontal axis represents the output
voltage. From this V-I diagram you can determine how the
driver reacts to any static load.
---------------------------------------------------------
Figures for this article appear in the .html version at:
www.sigcon.com/Pubs/news/8_07.htm
Figure 1: The V-I curve for a driver defines its behavior at
all voltages.
---------------------------------------------------------
NOTE: The top of my V-I chart depicts positive current
(sourced from the driver), and the bottom shows negative
(sinking) current. Occasionally you may encounter a data sheet
that defines the polarity of current in the reverse direction
(source current being negative), or a chart that reverses the
current and voltage axis. Always check the labels to make sure
you understand the orientation. I have marked IOH(+) and
IOL(-) on the vertical axis to remind you of my convention for
current.
The diagram displays two curves. The top curve (green)
illustrates the relation of current to voltage for this driver
when switched into the high state. This is a static curve,
showing the behavior at DC. It is derived by connecting the
driver to a load that draws progressively more and more
current from the driver, over a very slow scale of time, and
making a record of the driver output voltage at each
particular current. Then the driver is switched to a low
state, and the experiment repeated (purple curve).
This same V-I information may be encoded in a standard form
called an IBIS model. An IBIS model holds, at a minimum, the
high-state and low-state static V-I curves for a driver, plus
some information about how quickly the driver morphs from one
state to the other. Issues you may have heard about related to
the accuracy of IBIS modeling have to do with the form and
quality of the information used to morph the V-I curves from
low to high (or vice versa) during a fast switching transient,
the effects of packaging parasitics, and the lack of
information within an IBIS model about cross-coupling between
drivers within the same package (SSO noise). Still, I like
IBIS models and find them useful.
A typical driver specification calls out only a couple of
points along the V-I curves. If we are talking about a CMOS
totem-pole driver, you are expected to know that the gate
switches fully rail to rail in the absence of DC loading. In
the V-I domain, this implies that the high-state curve
includes the point [VCC,0], meaning the voltage floats all the
way up to VCC when you draw zero current from the driver. In
the diagram, the green curve crosses the horizontal axis at
the point [VCC,0].
Starting from the point [VCC,0] on the green curve, as you
pull progressively more current from the driver (moving up)
the output droops (moving to the left), with the result that
the high-state V-I curves for CMOS totem-pole drivers always
move up and to the left away from point [VCC,0].
Near VCC, the slope of the V-I curve (the localized delta-V
divided by delta-I) is defined as the "output resistance" of
the driver, R[ACTUAL]. For problems involving late reflections
that return to the source long after the source has switched
to a voltage above VOH, the value R[ACTUAL] determines the
behavior of the driver at that point in time.
A typical datasheet specification calls out only one point in
the high state. That point, [VOH,IOH], guarantees that the
high-state V-I curve, on its way up and to the left away from
[VCC,0], will always pass to the right side of the point
[VOH,IOH] (marked "A" in the diagram).
The diagram illustrates the slope of the wimpiest possible
driver (i.e., highest possible output resistance) that barely
meets this specification. That resistance, marked R[MAX], can
be calculated:
R[MAX] = (VCC-VOH) / IOH
When working through this formula use the minimum allowed
value of VCC for your driver. The driver has to still meet VOH
at the specified IOH current under this condition. The output
resistance will likely be no greater than that amount under
other conditions of VCC.
The maximum output resistance in the low state is simply
(VOL/IOL). Watch out for the polarity of current definitions
on the specification sheet-a "sinking current" of 8 mA means
an IOL of negative 8 mA.
Ed, your question had to do with the behavior of a driver when
connected to a big clump of capacitance. I will assume the
capacitance is all locally connected, at a distance of much
less than one rise time from the driver, so we may treat it as
a lumped-element load.
To determine the rise time of a large capacitive load we have
to know how much current comes out of the driver at voltages
other than VOH. For example, it would be nice to know the
short-circuit current when switched to the high state. This
current is the point where the high-state V-I curve crosses
the vertical axis (VOUT=0). If you knew that, and assuming the
V-I curve were at least concave down (no undulations), then a
straight-line approximation drawn from [0,ISHORT] to [VCC,0]
would yield a 90% rise time of:
TR = 2.3*(VCC/ISHORT)*CLOAD
Where VCC is the minimum allowed value of VCC, ISHORT is
the short-circuit current in Amps at that power-supply
voltage, and CLOAD is the total load capacitance in
farads.
This formula models the high-state V-I curve as a simple
straight line passing from [VCC,0] to the short-circuit point
[0,ISHORT]. In other words, for the purpose of first-order
modeling, you may replace the driver with a single equivalent
linear resistance having a value of VCC/ISHORT.
I happen to know that it takes 2.3 times the natural R-C time
constant for the step response of an R-C circuit to pass from
zero to the 90% response point. The formula therefore reads,
"2.3 times the product of the source resistance (VCC/ISHORT)
times the load capacitance (CLOAD)."
In a real circuit, the actual V-I curve for your driver
exceeds the straight-line approximation everywhere (because a
real high-state V-I curve is concave-down). The real driver
therefore pumps out more current than assumed by the straight-
line approximation, so the actual response time in a real
circuit will be less, sometimes considerably less, than the
simple estimate shown above. Any IBIS-model simulator can
demonstrate that effect.
Now we come to an interesting facet of your question that
concerns the maximum safe output current for a driver. First I
will deal with the DC effects of massive current.
For many CMOS totem-pole drivers, you can short the outputs to
ground for brief periods of time without damaging the driver.
Damage to a driver under a static shorted condition is caused
mostly by heating due to the excessive current. As long as the
short circuit does not persist, no harm is done. Because CMOS
drivers go into a current-limiting state as you pull more
current from them (i.e., the output curve is concave down,
flattening out as you approach short-circuit conditions), the
CMOS output stage is somewhat self-protecting.
The output stage of a PECL driver, on the other hand, has no
current-limiting feature. Without and special protection
circuitry, PECL outputs are easily destroyed by unintentional
grounding.
Finally, let's look at the effects of large AC currents. These
effects have to do with simultaneously switching output noise
(SSO noise). If you are not familiar with that topic check out
these recent articles:
"BGA Crosstalk (Xilinx Virtex-4 FPGA)", Newsletter vol. 8 #3
www.sigcon.com/Pubs/news/8_03.htm
"Spread Your Returns", EDN, March 31, 2005,
www.sigcon.com/Pubs/edn/SpreadYourReturns.htm
In brief, SSO noise is property of every IC package. When the
outputs of your IC switch, self-coupling within the IC package
couples a certain amount of noise back into your IC inputs. If
the noise is sufficiently large, it causes data errors at the
inputs. The same SSO noise effect also produces undesirable
glitches in your IC outputs.
The main factors that affect SSO noise are (1) the aggregate
amount of current switched by your IC, (2) the rise time of
that current, and (3) the number and quality of the power and
ground connections provided in the IC package. Most relevant
to this discussion is the total amount of current-more
capacitive loading enlarges that current, increasing the
amplitude of SSO noise.
An IC manufacturer is supposed to guarantee that, as long as
you live within the loading guidelines published for their IC,
you can switch any combination of outputs at will without
causing SSO errors. This guarantee is enforced by
incorporating an adequate number of power and ground pins, and
possibly also solid plane layers, bypass capacitors and other
features, into the IC package.
Do you suppose there is much SSO noise margin left in a
typical IC package design? Can you safely exceed the loading
guidelines without causing SSO errors? I doubt it. In a large
package already crammed with oodles of power and ground pins,
if there were any margin left for SSO noise the manufacturer
would likely have shaved off a few of the power and ground
pins to reduce the size and cost of the package. In fact, some
packages carry specific limitations on how many outputs can be
heavily loaded, or how many can be allowed to switch at any
one given time.
If you exceed the loading guidelines, burdening each output
with huge gobs of load capacitance, you will probably not
damage the driver, but you may create excessive amounts of SSO
noise, enough to induce data errors on your inputs.
My comments here refer to the undesirable practice of
connecting gobs of capacitance locally to your driver, all
located within a small fraction of one rise time of the
driver. If you spread your many loads along a transmission
structure with a uniform spacing of, say, 1/3 rise time
between each load, then your driver need not charge all the
loads at once. Spreading the loads in this manner reduces the
peak current required of the driver (and thus limits the SSO
noise). That is the secret to successfully driving many, many
loads.
Best Regards,
Dr. Howard Johnson
______________________________________________________
Join my upcoming seminars in San Jose, CA Jan 30-Feb 3, 2006.
A full schedule of cities and dates appears at:
www.sigcon.com.
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