[haiku-commits] r41028 - in haiku/trunk/src/add-ons: accelerants/radeon_hd kernel/drivers/graphics/radeon_hd
- From: kallisti5@xxxxxxxxxxx
- To: haiku-commits@xxxxxxxxxxxxx
- Date: Sat, 19 Mar 2011 19:49:15 +0100 (CET)
Author: kallisti5
Date: 2011-03-19 19:49:14 +0100 (Sat, 19 Mar 2011)
New Revision: 41028
Changeset: https://dev.haiku-os.org/changeset/41028
Modified:
haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.h
haiku/trunk/src/add-ons/accelerants/radeon_hd/engine.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/hooks.cpp
haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.h
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
Log:
pre-work style cleanup; no functional change
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
2011-03-19 16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.cpp
2011-03-19 18:49:14 UTC (rev 41028)
@@ -35,18 +35,18 @@
class AreaCloner {
public:
- AreaCloner();
- ~AreaCloner();
+ AreaCloner();
+ ~AreaCloner();
- area_id Clone(const char *name, void
**_address,
- uint32 spec,
uint32 protection,
- area_id
sourceArea);
- status_t InitCheck()
- { return fArea
< 0 ? (status_t)fArea : B_OK; }
- void Keep();
+ area_id Clone(const char *name,
void **_address,
+ uint32
spec, uint32 protection,
+ area_id
sourceArea);
+ status_t InitCheck()
+ {return
fArea < 0 ? (status_t)fArea : B_OK;}
+ void Keep();
private:
- area_id fArea;
+ area_id fArea;
};
@@ -118,8 +118,8 @@
status_t status = sharedCloner.InitCheck();
if (status < B_OK) {
free(gInfo);
- TRACE(("radeon_init_accelerant() failed shared area%i, %i\n",
data.shared_info_area,
- gInfo->shared_info_area));
+ TRACE(("radeon_init_accelerant() failed shared area%i, %i\n",
+ data.shared_info_area, gInfo->shared_info_area));
return status;
}
@@ -132,7 +132,7 @@
free(gInfo);
return status;
}
-
+
sharedCloner.Keep();
regsCloner.Keep();
@@ -194,9 +194,9 @@
radeon_uninit_accelerant(void)
{
TRACE(("radeon_uninit_accelerant()\n"));
-
+
gInfo->mode_list = NULL;
-
+
radeon_shared_info &info = *gInfo->shared_info;
uninit_lock(&info.accelerant_lock);
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.h
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.h 2011-03-19
16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/accelerant.h 2011-03-19
18:49:14 UTC (rev 41028)
@@ -50,13 +50,15 @@
return *(volatile uint32 *)(gInfo->regs + offset);
}
+
inline void
write32(uint32 offset, uint32 value)
{
*(volatile uint32 *)(gInfo->regs + offset) = value;
}
-// modes.cpp
+
+// modes.cpp
extern status_t create_mode_list(void);
#endif /* RADEON_HD_ACCELERANT_H */
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/engine.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/engine.cpp 2011-03-19
16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/engine.cpp 2011-03-19
18:49:14 UTC (rev 41028)
@@ -30,8 +30,8 @@
status_t
-radeon_acquire_engine(uint32 capabilities, uint32 maxWait, sync_token
*syncToken,
- engine_token **_engineToken)
+radeon_acquire_engine(uint32 capabilities, uint32 maxWait,
+ sync_token *syncToken, engine_token **_engineToken)
{
TRACE(("radeon_acquire_engine()\n"));
*_engineToken = &sEngineToken;
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/hooks.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/hooks.cpp 2011-03-19
16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/hooks.cpp 2011-03-19
18:49:14 UTC (rev 41028)
@@ -45,7 +45,7 @@
return (void*)radeon_get_frame_buffer_config;
case B_GET_PIXEL_CLOCK_LIMITS:
return (void*)radeon_get_pixel_clock_limits;
-
+
case B_ACQUIRE_ENGINE:
return (void*)radeon_acquire_engine;
case B_RELEASE_ENGINE:
Modified: haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp
===================================================================
--- haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-03-19
16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/accelerants/radeon_hd/mode.cpp 2011-03-19
18:49:14 UTC (rev 41028)
@@ -38,27 +38,30 @@
status_t
create_mode_list(void)
{
+ // TODO : Read active monitor EDID
+
+ /* Populate modeline with temporary example */
gDisplayMode.timing.pixel_clock = 71500;
- gDisplayMode.timing.h_display = 1366;
/* in pixels (not character clocks) */
+ gDisplayMode.timing.h_display = 1366; // In Pixels
gDisplayMode.timing.h_sync_start = 1406;
gDisplayMode.timing.h_sync_end = 1438;
gDisplayMode.timing.h_total = 1510;
- gDisplayMode.timing.v_display = 768;
/* in lines */
+ gDisplayMode.timing.v_display = 768; // In Pixels
gDisplayMode.timing.v_sync_start = 771;
gDisplayMode.timing.v_sync_end = 777;
gDisplayMode.timing.v_total = 789;
- gDisplayMode.timing.flags = 0;
/* sync polarity, etc. */
+ gDisplayMode.timing.flags = 0; // Polarity, ex:
B_POSITIVE_HSYNC
- gDisplayMode.space = B_RGB32_LITTLE; /*
pixel configuration */
- gDisplayMode.virtual_width = 1366; /* in pixels */
- gDisplayMode.virtual_height = 768; /* in lines */
- gDisplayMode.h_display_start = 0; /* first displayed pixel in
line */
- gDisplayMode.v_display_start = 0; /* first displayed line */
- gDisplayMode.flags = 0; /* mode flags (Some
drivers use this */
+ gDisplayMode.space = B_RGB32_LITTLE; // Pixel configuration
+ gDisplayMode.virtual_width = 1366; // In Pixels
+ gDisplayMode.virtual_height = 768; // In Pixels
+ gDisplayMode.h_display_start = 0;
+ gDisplayMode.v_display_start = 0;
+ gDisplayMode.flags = 0; // Mode flags
(Some drivers use this
- gInfo->mode_list = &gDisplayMode;
+ gInfo->mode_list = &gDisplayMode;
gInfo->shared_info->mode_count = 1;
- return B_OK;
+ return B_OK;
}
@@ -69,7 +72,7 @@
radeon_accelerant_mode_count(void)
{
TRACE(("radeon_accelerant_mode_count()\n"));
-
+
return gInfo->shared_info->mode_count;
}
@@ -87,74 +90,74 @@
inline void
write32AtMask(uint32 adress, uint32 value, uint32 mask)
{
- uint32 temp;
- temp = read32(adress);
- temp &= ~mask;
- temp |= value & mask;
- write32(adress, temp);
+ uint32 temp;
+ temp = read32(adress);
+ temp &= ~mask;
+ temp |= value & mask;
+ write32(adress, temp);
}
enum {
/* CRTC1 registers */
- D1CRTC_H_TOTAL = 0x6000,
- D1CRTC_H_BLANK_START_END = 0x6004,
- D1CRTC_H_SYNC_A = 0x6008,
- D1CRTC_H_SYNC_A_CNTL = 0x600C,
- D1CRTC_H_SYNC_B = 0x6010,
- D1CRTC_H_SYNC_B_CNTL = 0x6014,
+ D1CRTC_H_TOTAL = 0x6000,
+ D1CRTC_H_BLANK_START_END = 0x6004,
+ D1CRTC_H_SYNC_A = 0x6008,
+ D1CRTC_H_SYNC_A_CNTL = 0x600C,
+ D1CRTC_H_SYNC_B = 0x6010,
+ D1CRTC_H_SYNC_B_CNTL = 0x6014,
- D1CRTC_V_TOTAL = 0x6020,
- D1CRTC_V_BLANK_START_END = 0x6024,
- D1CRTC_V_SYNC_A = 0x6028,
- D1CRTC_V_SYNC_A_CNTL = 0x602C,
- D1CRTC_V_SYNC_B = 0x6030,
- D1CRTC_V_SYNC_B_CNTL = 0x6034,
+ D1CRTC_V_TOTAL = 0x6020,
+ D1CRTC_V_BLANK_START_END = 0x6024,
+ D1CRTC_V_SYNC_A = 0x6028,
+ D1CRTC_V_SYNC_A_CNTL = 0x602C,
+ D1CRTC_V_SYNC_B = 0x6030,
+ D1CRTC_V_SYNC_B_CNTL = 0x6034,
- D1CRTC_CONTROL = 0x6080,
- D1CRTC_BLANK_CONTROL = 0x6084,
- D1CRTC_INTERLACE_CONTROL = 0x6088,
- D1CRTC_BLACK_COLOR = 0x6098,
- D1CRTC_STATUS = 0x609C,
- D1CRTC_COUNT_CONTROL = 0x60B4,
-
+ D1CRTC_CONTROL = 0x6080,
+ D1CRTC_BLANK_CONTROL = 0x6084,
+ D1CRTC_INTERLACE_CONTROL = 0x6088,
+ D1CRTC_BLACK_COLOR = 0x6098,
+ D1CRTC_STATUS = 0x609C,
+ D1CRTC_COUNT_CONTROL = 0x60B4,
+
/* D1GRPH registers */
- D1GRPH_ENABLE = 0x6100,
- D1GRPH_CONTROL = 0x6104,
- D1GRPH_LUT_SEL = 0x6108,
- D1GRPH_SWAP_CNTL = 0x610C,
- D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
- D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118,
- D1GRPH_PITCH = 0x6120,
- D1GRPH_SURFACE_OFFSET_X = 0x6124,
- D1GRPH_SURFACE_OFFSET_Y = 0x6128,
- D1GRPH_X_START = 0x612C,
- D1GRPH_Y_START = 0x6130,
- D1GRPH_X_END = 0x6134,
- D1GRPH_Y_END = 0x6138,
- D1GRPH_UPDATE = 0x6144,
-
- /* D1MODE */
- D1MODE_DESKTOP_HEIGHT = 0x652C,
- D1MODE_VLINE_START_END = 0x6538,
- D1MODE_VLINE_STATUS = 0x653C,
- D1MODE_VIEWPORT_START = 0x6580,
- D1MODE_VIEWPORT_SIZE = 0x6584,
- D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588,
- D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C,
- D1MODE_DATA_FORMAT = 0x6528,
-
- /* D1SCL */
- D1SCL_ENABLE = 0x6590,
- D1SCL_TAP_CONTROL = 0x6594,
- D1MODE_CENTER = 0x659C, /* guess */
- D1SCL_HVSCALE = 0x65A4, /* guess */
- D1SCL_HFILTER = 0x65B0, /* guess */
- D1SCL_VFILTER = 0x65C0, /* guess */
- D1SCL_UPDATE = 0x65CC,
- D1SCL_DITHER = 0x65D4, /* guess */
- D1SCL_FLIP_CONTROL = 0x65D8 /* guess */
-
+ D1GRPH_ENABLE = 0x6100,
+ D1GRPH_CONTROL = 0x6104,
+ D1GRPH_LUT_SEL = 0x6108,
+ D1GRPH_SWAP_CNTL = 0x610C,
+ D1GRPH_PRIMARY_SURFACE_ADDRESS = 0x6110,
+ D1GRPH_SECONDARY_SURFACE_ADDRESS = 0x6118,
+ D1GRPH_PITCH = 0x6120,
+ D1GRPH_SURFACE_OFFSET_X = 0x6124,
+ D1GRPH_SURFACE_OFFSET_Y = 0x6128,
+ D1GRPH_X_START = 0x612C,
+ D1GRPH_Y_START = 0x6130,
+ D1GRPH_X_END = 0x6134,
+ D1GRPH_Y_END = 0x6138,
+ D1GRPH_UPDATE = 0x6144,
+
+ /* D1MODE */
+ D1MODE_DESKTOP_HEIGHT = 0x652C,
+ D1MODE_VLINE_START_END = 0x6538,
+ D1MODE_VLINE_STATUS = 0x653C,
+ D1MODE_VIEWPORT_START = 0x6580,
+ D1MODE_VIEWPORT_SIZE = 0x6584,
+ D1MODE_EXT_OVERSCAN_LEFT_RIGHT = 0x6588,
+ D1MODE_EXT_OVERSCAN_TOP_BOTTOM = 0x658C,
+ D1MODE_DATA_FORMAT = 0x6528,
+
+ /* D1SCL */
+ D1SCL_ENABLE = 0x6590,
+ D1SCL_TAP_CONTROL = 0x6594,
+ D1MODE_CENTER = 0x659C, /* guess */
+ D1SCL_HVSCALE = 0x65A4, /* guess */
+ D1SCL_HFILTER = 0x65B0, /* guess */
+ D1SCL_VFILTER = 0x65C0, /* guess */
+ D1SCL_UPDATE = 0x65CC,
+ D1SCL_DITHER = 0x65D4, /* guess */
+ D1SCL_FLIP_CONTROL = 0x65D8 /* guess */
+
};
@@ -196,59 +199,62 @@
bytesPerRow = (bytesPerRow + 63) & ~63;
}
+
#define D1_REG_OFFSET 0x0000
#define D2_REG_OFFSET 0x0800
-
+
static void
DxModeSet(display_mode *mode)
{
- uint32 regOffset = D1_REG_OFFSET;
+ uint32 regOffset = D1_REG_OFFSET;
display_timing& displayTiming = mode->timing;
-
- /* enable read requests */
- write32AtMask(regOffset + D1CRTC_CONTROL, 0, 0x01000000);
- /* Horizontal */
- write32(regOffset + D1CRTC_H_TOTAL, displayTiming.h_total - 1);
-
- uint16 blankStart = displayTiming.h_display; //displayTiming.h_sync_end;
- uint16 blankEnd = displayTiming.h_sync_start;//displayTiming.h_total;
- // write32(regOffset + D1CRTC_H_BLANK_START_END,
- // blankStart | (blankEnd << 16));
+ /* enable read requests */
+ write32AtMask(regOffset + D1CRTC_CONTROL, 0, 0x01000000);
- write32(regOffset + D1CRTC_H_SYNC_A,
+ /* Horizontal */
+ write32(regOffset + D1CRTC_H_TOTAL, displayTiming.h_total - 1);
+
+ uint16 blankStart = displayTiming.h_display; //
displayTiming.h_sync_end;
+ uint16 blankEnd = displayTiming.h_sync_start; //
displayTiming.h_total;
+// write32(regOffset + D1CRTC_H_BLANK_START_END,
+// blankStart | (blankEnd << 16));
+
+ write32(regOffset + D1CRTC_H_SYNC_A,
(displayTiming.h_sync_end - displayTiming.h_sync_start) << 16);
- //write32(regOffset + D1CRTC_H_SYNC_A_CNTL, Mode->Flags & V_NHSYNC);
- //!!!write32(regOffset + D1CRTC_H_SYNC_A_CNTL, V_NHSYNC);
+// write32(regOffset + D1CRTC_H_SYNC_A_CNTL, Mode->Flags & V_NHSYNC);
+//! write32(regOffset + D1CRTC_H_SYNC_A_CNTL, V_NHSYNC);
- /* Vertical */
- write32(regOffset + D1CRTC_V_TOTAL, displayTiming.v_total - 1);
+ /* Vertical */
+ write32(regOffset + D1CRTC_V_TOTAL, displayTiming.v_total - 1);
- blankStart = displayTiming.v_display;//displayTiming.v_sync_end;
- blankEnd = displayTiming.v_sync_start;//displayTiming.v_total;
- // write32(regOffset + D1CRTC_V_BLANK_START_END,
- // blankStart | (blankEnd << 16));
+ blankStart = displayTiming.v_display; // displayTiming.v_sync_end;
+ blankEnd = displayTiming.v_sync_start; // displayTiming.v_total;
+// write32(regOffset + D1CRTC_V_BLANK_START_END,
+// blankStart | (blankEnd << 16));
- /* set interlaced */
- //if (Mode->Flags & V_INTERLACE) {
- if (0) {
- write32(regOffset + D1CRTC_INTERLACE_CONTROL, 0x1);
- write32(regOffset + D1MODE_DATA_FORMAT, 0x1);
- } else {
- write32(regOffset + D1CRTC_INTERLACE_CONTROL, 0x0);
- write32(regOffset + D1MODE_DATA_FORMAT, 0x0);
- }
+ /* set interlaced */
+// if (Mode->Flags & V_INTERLACE) {
+ if (0) {
+ write32(regOffset + D1CRTC_INTERLACE_CONTROL, 0x1);
+ write32(regOffset + D1MODE_DATA_FORMAT, 0x1);
+ } else {
+ write32(regOffset + D1CRTC_INTERLACE_CONTROL, 0x0);
+ write32(regOffset + D1MODE_DATA_FORMAT, 0x0);
+ }
- write32(regOffset + D1CRTC_V_SYNC_A,
+ write32(regOffset + D1CRTC_V_SYNC_A,
(displayTiming.v_sync_end - displayTiming.v_sync_start) << 16);
- //write32(regOffset + D1CRTC_V_SYNC_A_CNTL, Mode->Flags & V_NVSYNC);
- //!!!write32(regOffset + D1CRTC_V_SYNC_A_CNTL, V_NVSYNC);
+// write32(regOffset + D1CRTC_V_SYNC_A_CNTL, Mode->Flags & V_NVSYNC);
+//! write32(regOffset + D1CRTC_V_SYNC_A_CNTL, V_NVSYNC);
- /* set D1CRTC_HORZ_COUNT_BY2_EN to 0; should only be set to 1 on 30bpp DVI
modes */
- write32AtMask(regOffset + D1CRTC_COUNT_CONTROL, 0x0, 0x1);
+ /* set D1CRTC_HORZ_COUNT_BY2_EN to 0;
+ should only be set to 1 on 30bpp DVI modes
+ */
+ write32AtMask(regOffset + D1CRTC_COUNT_CONTROL, 0x0, 0x1);
}
@@ -257,37 +263,37 @@
DxModeScale(display_mode *mode)
{
uint32 regOffset = D1_REG_OFFSET;
-
+
/* D1Mode registers */
- write32(regOffset + D1MODE_VIEWPORT_SIZE,
+ write32(regOffset + D1MODE_VIEWPORT_SIZE,
mode->timing.v_display | (mode->timing.h_display << 16));
- write32(regOffset + D1MODE_VIEWPORT_START, 0);
+ write32(regOffset + D1MODE_VIEWPORT_START, 0);
- /* write32(regOffset + D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
+/* write32(regOffset + D1MODE_EXT_OVERSCAN_LEFT_RIGHT,
(Overscan.OverscanLeft << 16) | Overscan.OverscanRight);
- write32(regOffset + D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
+ write32(regOffset + D1MODE_EXT_OVERSCAN_TOP_BOTTOM,
(Overscan.OverscanTop << 16) | Overscan.OverscanBottom);
*/
- write32(regOffset + D1SCL_ENABLE, 0);
+ write32(regOffset + D1SCL_ENABLE, 0);
write32(regOffset + D1SCL_TAP_CONTROL, 0);
write32(regOffset + D1MODE_CENTER, 0);
}
-
-
+
+
status_t
radeon_set_display_mode(display_mode *mode)
{
DxModeSet(mode);
-
+
DxModeScale(mode);
uint32 colorMode, bytesPerRow, bitsPerPixel;
get_color_space_format(*mode, colorMode, bytesPerRow, bitsPerPixel);
uint32 regOffset = D1_REG_OFFSET;
-
- write32AtMask(regOffset + D1GRPH_ENABLE, 1, 0x00000001);
+ write32AtMask(regOffset + D1GRPH_ENABLE, 1, 0x00000001);
+
/* disable R/B swap, disable tiling, disable 16bit alpha, etc. */
write32(regOffset + D1GRPH_CONTROL, 0);
@@ -306,31 +312,31 @@
default:
write32AtMask(regOffset + D1GRPH_CONTROL, 0x000002, 0x00000703);
break;
- /* TODO: 64bpp ;p */
- }
+ /* TODO: 64bpp ;p */
+ }
- /* Make sure that we are not swapping colours around */
- //if (rhdPtr->ChipSet > RHD_R600)
+ /* Make sure that we are not swapping colours around */
+// if (rhdPtr->ChipSet > RHD_R600)
write32(regOffset + D1GRPH_SWAP_CNTL, 0);
- /* R5xx - RS690 case is GRPH_CONTROL bit 16 */
+ /* R5xx - RS690 case is GRPH_CONTROL bit 16 */
#define R6XX_CONFIG_FB_BASE 0x542C /* AKA CONFIG_F0_BASE */
uint32 fbIntAddress = read32(R6XX_CONFIG_FB_BASE);
-
+
uint32 offset = gInfo->shared_info->frame_buffer_offset;
- write32(regOffset + D1GRPH_PRIMARY_SURFACE_ADDRESS,
+ write32(regOffset + D1GRPH_PRIMARY_SURFACE_ADDRESS,
fbIntAddress + offset);
- write32(regOffset + D1GRPH_PITCH, bytesPerRow / 4);
- write32(regOffset + D1GRPH_SURFACE_OFFSET_X, 0);
- write32(regOffset + D1GRPH_SURFACE_OFFSET_Y, 0);
- write32(regOffset + D1GRPH_X_START, 0);
- write32(regOffset + D1GRPH_Y_START, 0);
- write32(regOffset + D1GRPH_X_END, mode->virtual_width);
- write32(regOffset + D1GRPH_Y_END, mode->virtual_height);
+ write32(regOffset + D1GRPH_PITCH, bytesPerRow / 4);
+ write32(regOffset + D1GRPH_SURFACE_OFFSET_X, 0);
+ write32(regOffset + D1GRPH_SURFACE_OFFSET_Y, 0);
+ write32(regOffset + D1GRPH_X_START, 0);
+ write32(regOffset + D1GRPH_Y_START, 0);
+ write32(regOffset + D1GRPH_X_END, mode->virtual_width);
+ write32(regOffset + D1GRPH_Y_END, mode->virtual_height);
- /* D1Mode registers */
- write32(regOffset + D1MODE_DESKTOP_HEIGHT, mode->virtual_height);
+ /* D1Mode registers */
+ write32(regOffset + D1MODE_DESKTOP_HEIGHT, mode->virtual_height);
// update shared info
gInfo->shared_info->bytes_per_row = bytesPerRow;
@@ -340,7 +346,7 @@
return B_OK;
}
-
+
status_t
radeon_get_display_mode(display_mode *_currentMode)
{
Modified: haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp
===================================================================
--- haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp
2011-03-19 16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/device.cpp
2011-03-19 18:49:14 UTC (rev 41028)
@@ -39,9 +39,12 @@
static status_t device_open(const char *name, uint32 flags, void **_cookie);
static status_t device_close(void *data);
static status_t device_free(void *data);
-static status_t device_ioctl(void *data, uint32 opcode, void *buffer, size_t
length);
-static status_t device_read(void *data, off_t offset, void *buffer, size_t
*length);
-static status_t device_write(void *data, off_t offset, const void *buffer,
size_t *length);
+static status_t device_ioctl(void *data, uint32 opcode,
+ void *buffer, size_t length);
+static status_t device_read(void *data, off_t offset,
+ void *buffer, size_t *length);
+static status_t device_write(void *data, off_t offset,
+ const void *buffer, size_t *length);
device_hooks gDeviceHooks = {
@@ -207,7 +210,8 @@
static status_t
-device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length)
+device_read(void */*data*/, off_t /*pos*/,
+ void */*buffer*/, size_t *_length)
{
*_length = 0;
return B_NOT_ALLOWED;
@@ -215,7 +219,8 @@
static status_t
-device_write(void */*data*/, off_t /*pos*/, const void */*buffer*/, size_t
*_length)
+device_write(void */*data*/, off_t /*pos*/,
+ const void */*buffer*/, size_t *_length)
{
*_length = 0;
return B_NOT_ALLOWED;
Modified: haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp
===================================================================
--- haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp
2011-03-19 16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.cpp
2011-03-19 18:49:14 UTC (rev 41028)
@@ -137,7 +137,7 @@
{
TRACE((DEVICE_NAME ": init_hardware()\n"));
- status_t status = get_module(B_PCI_MODULE_NAME,(module_info **)&gPCI);
+ status_t status = get_module(B_PCI_MODULE_NAME, (module_info **)&gPCI);
if (status != B_OK) {
TRACE((DEVICE_NAME ": pci module unavailable\n"));
return status;
Modified: haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.h
===================================================================
--- haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.h
2011-03-19 16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/driver.h
2011-03-19 18:49:14 UTC (rev 41028)
@@ -50,4 +50,6 @@
size, value);
}
+
#endif /* DRIVER_H */
+
Modified:
haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
===================================================================
--- haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
2011-03-19 16:38:30 UTC (rev 41027)
+++ haiku/trunk/src/add-ons/kernel/drivers/graphics/radeon_hd/radeon_hd.cpp
2011-03-19 18:49:14 UTC (rev 41028)
@@ -42,8 +42,9 @@
status_t
radeon_hd_init(radeon_info &info)
{
+ TRACE((DEVICE_NAME ": radeon_hd_init() called\n"));
+
// memory mapped I/O
-
AreaKeeper sharedCreator;
info.shared_area = sharedCreator.Create("radeon hd shared info",
(void **)&info.shared_info, B_ANY_KERNEL_ADDRESS,
@@ -75,20 +76,21 @@
dprintf(DEVICE_NAME ": could not map framebuffer!\n");
return info.framebuffer_area;
}
-
+
// Turn on write combining for the area
vm_set_area_memory_type(info.framebuffer_area,
info.pci->u.h0.base_registers[RHD_FB_BAR], B_MTR_WC);
-
+
sharedCreator.Detach();
mmioMapper.Detach();
frambufferMapper.Detach();
info.shared_info->registers_area = info.registers_area;
info.shared_info->frame_buffer_offset = 0;
- info.shared_info->physical_graphics_memory =
info.pci->u.h0.base_registers[RHD_FB_BAR];
+ info.shared_info->physical_graphics_memory
+ = info.pci->u.h0.base_registers[RHD_FB_BAR];
- TRACE((DEVICE_NAME "radeon_hd_init() completed successfully!\n"));
+ TRACE((DEVICE_NAME ": radeon_hd_init() completed successfully!\n"));
return B_OK;
}
Other related posts:
- » [haiku-commits] r41028 - in haiku/trunk/src/add-ons: accelerants/radeon_hd kernel/drivers/graphics/radeon_hd - kallisti5
