hrev49694 adds 1 changeset to branch 'master'
old head: 990845d3c2c71f1accc14c3b74e4915e283c0f2e
new head: 97aa078ef4033692e70b1f95e7a62581bcbe518a
overview:
http://cgit.haiku-os.org/haiku/log/?qt=range&q=97aa078ef403+%5E990845d3c2c7
----------------------------------------------------------------------------
97aa078ef403: intel_extreme: Intial work for ValleyView support
* No impact to non-ValleyView chipsets
* Bump some register locations for VLV
* Only have HDMI port to test with on my ValleyView GPU
and our driver seems to be missing all HDMI and
sideband functionality.
* As ValleyView chipsets seem to be UEFI only, we don't
have VESA fallback, so this shouldn't cause regressions.
(unless we get UEFI framebuffer support)
[ Alexander von Gluck IV <kallisti5@xxxxxxxxxxx> ]
----------------------------------------------------------------------------
Revision: hrev49694
Commit: 97aa078ef4033692e70b1f95e7a62581bcbe518a
URL: http://cgit.haiku-os.org/haiku/commit/?id=97aa078ef403
Author: Alexander von Gluck IV <kallisti5@xxxxxxxxxxx>
Date: Fri Oct 16 04:37:18 2015 UTC
----------------------------------------------------------------------------
7 files changed, 56 insertions(+), 9 deletions(-)
.../private/graphics/intel_extreme/intel_extreme.h | 17 ++++++++++++-----
src/add-ons/accelerants/intel_extreme/hooks.cpp | 3 ++-
src/add-ons/accelerants/intel_extreme/mode.cpp | 7 +++++--
src/add-ons/kernel/busses/agp_gart/intel_gart.cpp | 17 +++++++++++++++++
.../drivers/graphics/intel_extreme/driver.cpp | 7 +++++++
.../graphics/intel_extreme/intel_extreme.cpp | 9 +++++++++
.../kernel/drivers/graphics/intel_extreme/power.cpp | 5 ++++-
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h
b/headers/private/graphics/intel_extreme/intel_extreme.h
index 1703898..7145aeb 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -39,6 +39,7 @@
#define INTEL_TYPE_ILK (INTEL_TYPE_9xx | 0x1000)
#define INTEL_TYPE_SNB (INTEL_TYPE_9xx | 0x2000)
#define INTEL_TYPE_IVB (INTEL_TYPE_9xx | 0x4000)
+#define INTEL_TYPE_VLV (INTEL_TYPE_9xx | 0x8000)
// models
#define INTEL_TYPE_SERVER 0x0004
#define INTEL_TYPE_MOBILE 0x0008
@@ -61,6 +62,11 @@
#define INTEL_TYPE_IVBG (INTEL_TYPE_IVB)
#define INTEL_TYPE_IVBGM (INTEL_TYPE_IVB | INTEL_TYPE_MOBILE)
#define INTEL_TYPE_IVBGS (INTEL_TYPE_IVB | INTEL_TYPE_SERVER)
+#define INTEL_TYPE_VLVG (INTEL_TYPE_VLV)
+#define INTEL_TYPE_VLVGM (INTEL_TYPE_VLV | INTEL_TYPE_MOBILE)
+
+// ValleyView MMIO offset
+#define VLV_DISPLAY_BASE 0x180000
#define DEVICE_NAME "intel_extreme"
#define INTEL_ACCELERANT_NAME "intel_extreme.accelerant"
@@ -131,7 +137,7 @@ struct DeviceType {
bool HasPlatformControlHub() const
{
return InGroup(INTEL_TYPE_ILK) || InGroup(INTEL_TYPE_SNB)
- || InGroup(INTEL_TYPE_IVB);
+ || InGroup(INTEL_TYPE_IVB) || InGroup(INTEL_TYPE_VLV);
}
};
@@ -166,6 +172,7 @@ struct intel_shared_info {
area_id registers_area; // area of
memory mapped registers
uint32 register_blocks[REGISTER_BLOCK_COUNT];
+
uint8* status_page;
phys_addr_t physical_status_page;
uint8* graphics_memory;
@@ -368,7 +375,6 @@ struct intel_free_graphics_memory {
#define PCH_INTERRUPT_VBLANK_PIPEB_SNB (1 << 15)
// display ports
-#define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 |
REGS_SOUTH_TRANSCODER_PORT)
#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
@@ -380,9 +386,6 @@ struct intel_free_graphics_memory {
#define DISPLAY_MONITOR_POLARITY_MASK (3UL << 3)
#define DISPLAY_MONITOR_POSITIVE_HSYNC (1UL << 3)
#define DISPLAY_MONITOR_POSITIVE_VSYNC (2UL << 3)
-#define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
-#define INTEL_DISPLAY_C_DIGITAL (0x1160 |
REGS_SOUTH_TRANSCODER_PORT)
-#define INTEL_DISPLAY_LVDS_PORT (0x1180 |
REGS_SOUTH_TRANSCODER_PORT)
#define LVDS_POST2_RATE_SLOW 14 // PLL Divisors
#define LVDS_POST2_RATE_FAST 7
#define LVDS_CLKB_POWER_MASK (3 << 4)
@@ -436,7 +439,11 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_IMAGE_SIZE (0x001c |
REGS_NORTH_PIPE_AND_PORT)
#define INTEL_DISPLAY_B_IMAGE_SIZE (0x101c |
REGS_NORTH_PIPE_AND_PORT)
+#define INTEL_DISPLAY_A_ANALOG_PORT (0x1100 |
REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_A_DIGITAL_PORT (0x1120 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISPLAY_B_DIGITAL_PORT (0x1140 | REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_C_DIGITAL (0x1160 |
REGS_SOUTH_TRANSCODER_PORT)
+#define INTEL_DISPLAY_LVDS_PORT (0x1180 |
REGS_SOUTH_TRANSCODER_PORT)
// planes
#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
diff --git a/src/add-ons/accelerants/intel_extreme/hooks.cpp
b/src/add-ons/accelerants/intel_extreme/hooks.cpp
index e97a8d7..975551b 100644
--- a/src/add-ons/accelerants/intel_extreme/hooks.cpp
+++ b/src/add-ons/accelerants/intel_extreme/hooks.cpp
@@ -118,7 +118,8 @@ get_accelerant_hook(uint32 feature, void* data)
||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD)
||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
- ||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB))
+ ||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
+ ||
gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV))
return NULL;
return (void*)intel_allocate_overlay_buffer;
diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp
b/src/add-ons/accelerants/intel_extreme/mode.cpp
index ca9b522..961356b 100755
--- a/src/add-ons/accelerants/intel_extreme/mode.cpp
+++ b/src/add-ons/accelerants/intel_extreme/mode.cpp
@@ -140,7 +140,8 @@ get_pll_limits(pll_limits &limits)
if (gInfo->shared_info->device_type.InGroup(INTEL_TYPE_ILK)
|| gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB)
- || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)) {
+ || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IVB)
+ || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV)) {
// TODO: support LVDS output limits as well
static const pll_limits kLimits = {
// p, p1, p2, high, n, m, m1, m2
@@ -351,6 +352,7 @@ retrieve_current_mode(display_mode& mode, uint32
pllRegister)
controlRegister = INTEL_DISPLAY_B_CONTROL;
} else {
// TODO: not supported
+ TRACE("%s: pllRegister not yet supported\n", __func__);
return;
}
@@ -565,7 +567,8 @@ set_frame_buffer_base()
|| sharedInfo.device_type.InGroup(INTEL_TYPE_G4x)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_ILK)
|| sharedInfo.device_type.InGroup(INTEL_TYPE_SNB)
- || sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)) {
+ || sharedInfo.device_type.InGroup(INTEL_TYPE_IVB)
+ || sharedInfo.device_type.InGroup(INTEL_TYPE_VLV)) {
write32(baseRegister, mode.v_display_start *
sharedInfo.bytes_per_row
+ mode.h_display_start * (sharedInfo.bits_per_pixel +
7) / 8);
read32(baseRegister);
diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
index 4618721..93b8271 100644
--- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
+++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp
@@ -1,6 +1,14 @@
/*
* Copyright 2008-2010, Axel Dörfler, axeld@xxxxxxxxxxxxxxxx.
+ * Copyright 2011-2015, Haiku, Inc. All Rights Reserved.
* Distributed under the terms of the MIT License.
+ *
+ * Authors:
+ * Axel Dörfler, axeld@xxxxxxxxxxxxxxxx
+ * Jerome Duval, jerome.duval@xxxxxxxxx
+ * Adrien Destugues, pulkomandy@xxxxxxxxx
+ * Michael Lotz, mmlr@xxxxxxxx
+ * Alexander von Gluck IV, kallisti5@xxxxxxxxxxx
*/
@@ -104,6 +112,14 @@ const struct supported_device {
{0x0c00, 0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
{0x0c04, 0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
{0x0d04, 0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+
+ // XXX: 0x0f00 only confirmed on 0x0f30, 0x0f31
+ {0x0f00, 0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
+ {0x0f00, 0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f00, 0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f00, 0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f00, 0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f00, 0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
};
struct intel_info {
@@ -392,6 +408,7 @@ intel_map(intel_info &info)
info.display.u.h0.base_registers[mmioIndex],
info.display.u.h0.base_register_sizes[mmioIndex],
B_ANY_KERNEL_ADDRESS,
B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA,
(void**)&info.registers);
+
if (mmioMapper.InitCheck() < B_OK) {
dprintf("agp_intel: could not map memory I/O!\n");
return info.registers_area;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
index d9f62fb..22dd3f0 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
@@ -100,6 +100,13 @@ const struct supported_device {
{0x0412, INTEL_TYPE_IVBG, "Haswell Desktop"},
{0x0416, INTEL_TYPE_IVBGM, "Haswell Mobile"},
{0x0d26, INTEL_TYPE_IVBGM, "Haswell Mobile"},
+
+ {0x0155, INTEL_TYPE_VLVG, "ValleyView Desktop"},
+ {0x0f30, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f31, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f32, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0f33, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
+ {0x0157, INTEL_TYPE_VLVGM, "ValleyView Mobile"},
};
int32 api_version = B_CUR_DRIVER_API_VERSION;
diff --git
a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index 204d52c..7637ab9 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -4,6 +4,7 @@
*
* Authors:
* Axel Dörfler, axeld@xxxxxxxxxxxxxxxx
+ * Alexander von Gluck IV, kallisti5@xxxxxxxxxxx
*/
@@ -345,6 +346,14 @@ intel_extreme_init(intel_info &info)
= ICH_PORT_REGISTER_BASE;
}
+ // "I nearly got violent with the hw guys when they told me..."
+ if (info.device_type.InFamily(INTEL_TYPE_VLV)) {
+ TRACE("%s: ValleyView MMIO offset engaged\n", __func__);
+ blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] +=
VLV_DISPLAY_BASE;
+ blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] += VLV_DISPLAY_BASE;
+ blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
+ }
+
// make sure bus master, memory-mapped I/O, and frame buffer is enabled
set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci,
PCI_command, 2) | PCI_command_io | PCI_command_memory
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
index 9c4f6c7..5864504 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/power.cpp
@@ -37,6 +37,9 @@ intel_en_gating(intel_info &info)
} else if (info.device_type.InGroup(INTEL_TYPE_IVB)) {
TRACE("IvyBridge clock gating\n");
write32(info, 0x42020, (1L << 28));
+ } else if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
+ TRACE("ValleyView clock gating\n");
+ write32(info, VLV_DISPLAY_BASE + 0x6200, (1L << 28));
} else if (info.device_type.InGroup(INTEL_TYPE_ILK)) {
TRACE("IronLake clock gating\n");
write32(info, 0x42020, (1L << 7) | (1L << 5));
@@ -172,4 +175,4 @@ intel_en_downclock(intel_info &info)
write32(info, INTEL6_PMINTRMSK, 0);
return B_OK;
-}
\ No newline at end of file
+}
