[haiku-bugs] Re: [Haiku] #3: PCI bus_manager does no memory resource assignment
- From: "Haiku" <trac@xxxxxxxxxxxx>
- To: undisclosed-recipients: ;
- Date: Sat, 26 Mar 2022 13:14:50 -0000
#3: PCI bus_manager does no memory resource assignment
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Reporter: marcusoverhagen | Owner: marcusoverhagen
Type: bug | Status: in-progress
Priority: high | Milestone: R1.1
Component: System/Kernel | Version: R1/Development
Resolution: | Keywords:
Blocked By: 6213 | Blocking:
Platform: All |
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Comment (by pulkomandy):
Sounds familiar. Is it still valid? was this for non acpi compliant
systems?
Yes, it's still valid.
During boot, the BIOS may or may not assign addresses to each device. You
can expect that basic devices (graphics, network, etc) will be initialized
because the BIOS needs them. Maybe they will assign addresses to
everything, but maybe not.
In the case where the BIOS didn't do it, we see that the BAR registers for
the affected device will still be 0 (this is visible in syslog when we
dump the PCI information). In this case it is up to us to figure out an
address for the device. The basic process is:
- Write FFFFFFFF to the BAR register
- Read back the register to know how much space the device needs, and if
it has constraints (memory or IO space, 32 or 64bit addressing,
prefetchable or not).
- Restore the initial value of the BAR register
We already do these steps in PCI::_GetBarInfo in the PCI bus manager.
After this step we are left with two types of devices:
- Those which are already mapped by the BIOS, will have an address in
their BAR registers already. Now we also know their size.
- Those which are not already mapped, will have an address of 0. We need
to allocate them an address and write it to the BAR register.
Now we need to figure out how to allocate that address. It must be in the
memory window of the PCI host controller. In the case of devices that are
accessed theough a pci-to-pci bridge, we get that info from the bridge,
which specifies which memory space it makes visible. However, in the case
of devices attached to the root of the PCI bus, it's not clear how we get
the info. Apparently it is platform specific and we know it from how we
located the PCI bus in the first place. On x86 we use ACPI for that. I
don't see where the info is in the ACPI table we use. If you look at the
RISC-V ECAM code you will see that it gets the info from the FDT there.
--
Ticket URL: <
https://dev.haiku-os.org/ticket/3#comment:10>
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