[gmpi] Re: multithreading host interface
- From: "Vincent Burel" <vincent.burel@xxxxxxxxxx>
- To: <gmpi@xxxxxxxxxxxxx>
- Date: Thu, 10 Apr 2003 09:56:21 +0200
----- Original Message -----
From: "Tim Hockin" <thockin@xxxxxxxxxx>
To: <gmpi@xxxxxxxxxxxxx>
Sent: Wednesday, April 09, 2003 8:32 PM
Subject: [gmpi] Re: multithreading host interface
> > > in particular, the trimedia processor in the pyramix has no access to
> > > the CPU cache - all data shared between them goes via non-cache
> > > memory.
> >
> > i'm sorry but on SMP system i don't think that processor share their
cache
> > memory with other ones. (or i want to see the press release with the
picture
> > of the electronician who did that).
>
> There's this thing called MESI - a cache-coherency protocol. On
> cache-coherent systems, if you write to your local cache, the other CPU(s)
> gets updated if it has that address cached. Not 'sharing' but coherent.
if i didn't know that , do you think that i would write that i write above.
:-)
24201606.pdf from Intel will help you to understand more again how the cache
can be coherent and what are the consequences.
> > > this means that indeed, "mov" is atomic.
> >
> > i don't follow you anymore :-) i don't see why it should be more atomic
than
> > in a SMP system... since i have to invalidate or writeback the cache...
or
>
> I don't know the system in discussion,
don't talk so ! :-)
>but if you write to non-cacheable memory,
non cacheable memory !!! new concept i guess !? :-) who talk about non
cacheable memory !?
> > Well, i just would like to share my method: the uni-directional
> > communication with an integer. One processor is always writing, while
the
> > other one is always reading. that's all...
>
> And that is fine on X86. It doesn't work on (for example) a SPARC.
:-)) funny ! to make a uni directionnal communication on int32 for example,
you need 3 conditions :
- A MOV or INC instruction cannot be stopped.
- The Cache Manager CANNOT invalidate or writeback less than 32bit.
- A processor CANNOT access to an address used by a cache operation.
now explain me where the SPARC does not respect one of these conditions !
> Nothing stops you from doing it your way, just don't expect your Plugin to
> work on all future platforms.
thanks you but please, don't worry about me.
Vincent Burel
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