[gmpi] Re: multithreading host interface
- From: Paul Davis <paul@xxxxxxxxxxxxxxxxxxxxx>
- To: gmpi@xxxxxxxxxxxxx
- Date: Wed, 09 Apr 2003 10:49:43 -0400
>Well, the Cache behavior is a different problem, which can be solved easily
>by using 2 integers, for the two directions of the communication... then
>there is no problem anymore, maybe you won't get the information exactely
>right now after the MOV, but after a cacheInvalidate or something like that.
sorry, but thats the whole point: you can't just write to an integer
and expect a thread running on another processor to see the correct
value. and note that your solution doesn't scale well: on a 32-way
system, you need 32 integers! insane? i think so :)
on many platforms, 32 bit integer access is atomic, but i have
recently read that there are even some newer SMP-x86 systems without
32-bit atomic access. this means that you have to wrap the operations
in a macro/inline function call. the linux kernel (to give just one
example) has widespread use of atomic_inc(), atomic_dec(),
atomic_set() etc, which on a vanilla x86 system resolve to regular old
32 bit reads and writes. on SMP SPARC systems, for example, they do
something a bit different. etc.
>it's the same on trimedia Philips (Pyramix). But there is again some trick
>which can stay consistent with one integer only, for example when one thread
>is always writing and the other one is always reading...
nope. the problem here is that values have to be coherent between two
(or more) *processors* not just threads. you have to have cache-coherency
because otherwise you have race conditions.
--p
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