[fabacad] 'Restrictive design rules' at 32-nm technology

  • From: Saif Abrar <saif.abrar@xxxxxxxxxxx>
  • To: Saif Abrar <saif.abrar@xxxxxxxxxxx>
  • Date: Wed, 12 Jul 2006 08:28:21 +0530

Analyst calls for 'restrictive design rules' at 32-nm--

SAN FRANCISCO â The semiconductor could see widespread adoption of
so-called "restrictive design rules" (RDR) as a way to ensure acceptable
yield and return on investment at the 32-nanometer node, according to Gary
Smith, a managing vice president and chief EDA analyst at Gartner Inc.

Speaking to a crowded hotel ballroom at the Semiconductor Equipment and
Materials International (SEMI) Market Symposium here Monday (July 10),
Smith said "four or five" large semiconductor companies, including IBM
Corp., are already working on RDR, or structured regular silicon, which
involves creating chips from wafers of pre-designed arrays of logic cells.

Similar in concept to FPGAs, the theory behind RDR, according to Smith, is
that a regular array is significantly easier to manufacture than a
semi-random array of cells.

RDR has been gaining steam in technical papers and presentations for the
past several years. According to Smith, RDR has been proven out at 45-nm by

Widespread adoption of RDR, which critics say could restrict innovation by
stifling designers' creativity, would require a radical change in mindset,
but according to Smith, may be the most efficient way to sidestep the
design-for-manufacturability (DFM) challenges that projected to
increasingly decimate yields at future nodes.

"When push comes to shove, when things get really hard, we change the
design methodology," Smith said. "We've done that a few times."

The forthcoming adoption of RDR, Smith said, is a replay of the design
situation in the 1970s, when many companies adopted the newly created ASIC
model, but custom design remained an option for some.

Smith told the crowd that DFM solutions offered by vendors so far have not
been aimed at actual design teams, but layout engineers. The concept of
yield awareness will eventually be embedded in physical design products
like place-and-route tools, he said. This, he said, has the potential to be
a driver for growth in IC CAD tools, which has stagnated in recent years.

A recent highly publicized introductions of a foundry process model by
Taiwan Semiconductor Manufacturing Co. (TSMC) has not solved the
fundamental problem of providing access to necessary process information to
the majority of fabless companies, Smith said. The model's encryption does
not provide enough security, Smith said, and TSMC has been wary of
providing the model to anyone but its largest customers, offering DFM
services to others instead.

"[Providing DFM services] is a very unnatural situation for the foundries,"
Smith said. "They don't like it at all. Basically they are becoming ASIC
vendors, and that's not what they want to do. But they are between a rock
and a hard place, because they don't want to give up their process model."

But Smith suggested that DFM tools may be a mere "band-aid" for the
industry, anyway. In order to move past roadblocks, Smith said, the
industry must adopt new EDA tools, process equipment or design
methodologies. For the past several technology nodes, the industry has
moved forward by changing EDA tools or process equipment, Smith said.

"EDA tools and/or semi equipment have saved the day for the last four
process nodes," Smith said. "For now, immersion lithography has saved the
day for 45-nm." But at 32-nm, the industry will likely be forced to address
"the silicon problem," he said.

Syed SAIF Abrar
Philips Towers, # 1, Murphy Road, Ulsoor, Bangalore-8, INDIA

Other related posts:

  • » [fabacad] 'Restrictive design rules' at 32-nm technology