[SI-LIST] Re: why "error: not increasing in time" in hspice?
- From: Pratap Narayan SINGH <pratap.singh@xxxxxx>
- To: jideguzi <jideguzi@xxxxxxx>
- Date: Tue, 27 May 2008 13:27:16 +0530
hi jideguzi,
Just try to increase your pwl last time stamp to 14n
and your problem will
be solved. Actually some mathematics of parameters is resulting in *_r
variables to 13.09..ns
which is more than the next time time stamp.
regards,
Pratap
jideguzi wrote:
> hi all
>
> I created a PWL source in my main circuit but when I run the netlist with
> hspice, it gives me error: **error** piecewise source 0:vdh
> not increasing in time
>I have tried many ways to modified it, but failed!
>is there anybody meet the same problem like that? who can tell me where I am
>making a mistake?
>
>
>my netlist codes:
> .tran 0.001n 18n UIC sweep DATA=INPUT_RAMP
>options autostop accurat runlvl
>ic v(dh)=vdd
>........
>param ckramp_l='9n-ckramp/2*1.25'
>param ckramp_r='9n+ckramp/2*1.25'
>param inramp_l='mid-inramp/2*1.25'
>param inramp_r='mid+inramp/2*1.25'
>.......
>
>vsel sel 0 pwl (0n vdd 'ckramp_l' vdd 'ckramp_r' 0 13n 0)
>vdh dh 0 pwl (0n vdd 'inramp_l' vdd 'inramp_r' 0 13n 0)
>
>DATA INPUT_RAMP
> inramp ckramp mid
> 0.015n 0.015n 13n
> 0.015n 0.015n 9n
> 0.015n 0.015n 5n
>ENDDATA
>
>
>
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--
Pratap Narayan Singh
MMC-IPD/Analog Mixed Signal
ST Microelectronics India
Plot No. 1, Knowledge Park III,
Greater Noida
Tina Ext: 3790
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