hi all I created a PWL source in my main circuit but when I run the netlist with hspice, it gives me error: **error** piecewise source 0:vdh not increasing in time I have tried many ways to modified it, but failed! is there anybody meet the same problem like that? who can tell me where I am making a mistake? my netlist codes: .tran 0.001n 18n UIC sweep DATA=INPUT_RAMP options autostop accurat runlvl ic v(dh)=vdd ........ param ckramp_l='9n-ckramp/2*1.25' param ckramp_r='9n+ckramp/2*1.25' param inramp_l='mid-inramp/2*1.25' param inramp_r='mid+inramp/2*1.25' ....... vsel sel 0 pwl (0n vdd 'ckramp_l' vdd 'ckramp_r' 0 13n 0) vdh dh 0 pwl (0n vdd 'inramp_l' vdd 'inramp_r' 0 13n 0) DATA INPUT_RAMP inramp ckramp mid 0.015n 0.015n 13n 0.015n 0.015n 9n 0.015n 0.015n 5n ENDDATA ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu