[SI-LIST] Re: six layer, eight layer, other
- From: steve weir <weirsp@xxxxxxxxxx>
- To: calaf_calaf_calaf@xxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Mon, 05 Jul 2004 12:19:53 -0700
calaf, as to layer count there are various ways to estimate the number that
will be necessary assuming you have placement flexibility. If you don't
have placement flexibility it gets tougher. Six voltages can be a bit
challenging, especially if you can't concentrate each.
Stack-up #1 doesn't look very good to me. It looks like an EMC nightmare
waiting to happen. It also looks unbalanced from a Cu standpoint and will
likely warp.
Stack-up #2 is better, but still not very appealing. Without more
information on just how much Cu you need for each of those five voltages it
is difficult to make a specific recommendation.
Maybe if the fill balances out right:
1 signal
2 gnd
3 routed power, signal
4 3.3V plane
5 gnd
6 routed power, signal
7 gnd
8 signal
Steve
At 11:56 AM 7/5/2004 +0000, calaf_calaf_calaf wrote:
>Hi everyone:
>I am trying a stack like this:
>1. signal
>2. gnd
>3. power & signal
>4. gnd
>5. power 3,3
>6. signal
>
>but I have many different powers and signals so it is hard to carried
>it out. The worst may be that it is tough to set 3.3V 2.5 and 1.2V in
>only two planes because all of them affect a BGA FPGA. Maybe it is
>necessary 8 layers, for example:
>
>1. signal
>2. gnd
>3. power 1.2V, 1.6V, signal
>4. signal
>5. power 2.5V, 5, signal
>6. gnd
>7. power 3.3
>8. signal
>
>What do you think?
>
>I will thank you any help
>Thanks and best regards
>
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