[SI-LIST] Re: return path
- From: steve weir <weirsi@xxxxxxxxxx>
- To: chrice102 <chrice102@xxxxxxxx>
- Date: Tue, 08 Apr 2008 03:33:59 -0700
chrice102 yes that is the only reason.
Steve
chrice102 wrote:
> hi steve
> thank you for your replies! in our motherboard system,the layers is S
> V G S.and we route the command and control signals on TOP layer.so we
> have to split vcc plane into vdd and gnd in ddr area.the DQ signal ref
> the gnd plane ,the command and control signal ref the vdd .you said
> "Vdd reference on address / control supports low cost PCBs.".this is
> the only reason?
> 2008-04-08
> ------------------------------------------------------------------------
> chrice102
> ------------------------------------------------------------------------
> *发件人：* steve weir
> *发送时间：* 2008-04-08 16:37:51
> *收件人：* chrice102
> *抄送：* si-list@xxxxxxxxxxxxx
> *主题：* Re: [SI-LIST] return path
> Vdd reference on address / control supports low cost PCBs.
> ODT on common lines requires enabling in one chip only via control
> registers. The address lines are used to access the control registers.
> Steve.
> chrice102 wrote:
> > hi all
> > I have some problems :In DDR system,the reference plane of ADDRS
> signals is Vddr,why isn't gnd plane? and why does the chip vendor also
> put the terminater of the ADDRS signal into the chip?
> > 2008-04-08
> >
> >
> >
> > chrice102
> >
> >
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> --
> Steve Weir
> Teraspeed Consulting Group LLC
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--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(866) 675-4630 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC
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