[SI-LIST] Re: problems about 1-to-2 FE connection
- From: steve weir <weirsp@xxxxxxxxxx>
- To: peter.zhu@xxxxxxxxxx, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 24 Dec 2003 03:45:22 -0800
Peter,
The MLT3 risetime is about 3-5ns. If the connection in the backplane is a
"T" of any length then the stub between the center and end of the T with
one card out is going to be a challenge.
If the wires are separate in the backplane, then an Ethernet analog mux on
the CPU card will solve your problems. If not, then the only viable choice
I see is to cut down the frequency content on the line with RC networks
between the PHY's and the transformers so that the stub does not ring too
badly.
Steve.
At 09:37 PM 12/23/2003 +0800, peter zhu wrote:
>Hi,experts:
>
>Very tough problem for me in Ethernet redundancy design.
>
>In our backplane, we use an illegal Ethernet switch board redundancy
>scheme. our processor board has one FE(Fast Ethernet), and two switch
>boards are resided in backplane for redundancy. the processor board FE
>connect to the two switch board at the same time, but one switch board is
>in standby state(The PHY on this board is tristated), so the processor
>board FE will communication with the active switch board. But you know, FE
>must have a transformer for isolation, so the processor board FE has
>1-to-2 transformer connection because of the two switch board on this FE.
>This will cause to Ethernt singal distortion and this is not compliant
>with standard, and some processor boards can not transmit data with very
>high speed.
>
>If we use AC104QF from Broadcom, maybe 2 boards FE will fail among 12
>boards, other 10 boards FE are very normal.
>
>But if we use AM79C875KI from AMD, maybe 5 boards FE will fail among 12
>boards.
>
>Our redundancy scheme is not changeable, so how to let the FE work nomal
>in this situation?
>Does anyone encounter similar problems?
>
>Urgent, I very appreciate your help and information.
>
>
>Thanks!
>
>Peter
>
>UTStarocm
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