[SI-LIST] diff pair routing at 10gig
- From: "Moshe Frid" <moshef@xxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 May 2007 11:18:40 +0300
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Hello all
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Can someone help me with routing issue of diff pair at 10gig from serdes
chip to XFP connector=20
I have 2 options -=20
1. Rout in outer layer (cs) without vias with solder mask cover
reference plane in layer 2 (the traces will go under the xfp cage would
it be a problem)
2. Rout it in inner layer in strip line between to planes but with 2
vias per line=20
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What should work best for me
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thanks
________________________________
Moshe Frid=20
Senior PCB Designer=20
Adcom Computers and Communications Ltd.
17 Ha'Tidhar st., Ra'anana
Israel 43665
Tel: +(972)-9-7417411 ext. 108
Fax: +(972)-9-7417422
Mobile: +(972)-54-6573232
E-mail: moshef@xxxxxxxxxxx
<http://www.adcom.co.il>=20
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