[SI-LIST] Re: decoupling capacitor placement/route
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jemanakk@xxxxxxxxxxxxxxxxxxx
- Date: Tue, 30 Mar 2010 18:54:20 -0700
Joseph,
Thin dielectric does not displace Farads. Thin dielectric reduces
Henries. With thin dielectric, you can shift inductance budget that
would have been consumed by X-Y plane spreading inductance into the
bypass capacitors. That is to say that you can use fewer caps to yield
the same impedance to the IC from about 5MHz on up to the cut-off
frequency either between the IC and the PDN, or the PDN discrete bypass
caps and the cavity planar capacitance.
Say for example you have a BGA connected to a 4 mil power / ground
cavity with a ring of power / ground pins. For the closest that you
could place capacitors around that part, assume that the spreading
inductance is 50pH. No matter how many capacitors you use, you will
never get the inductance below that 50pH. If you do a really good job
with conventional capacitors and the cavity is close to the PCB surface,
then ten of them could get you another 50pH for 100pH total for the
combination of the caps and the X-Y spreading inductance. Now, change
the cavity to 1 mil thick HK-04 or BC24 material. The cavity inductance
drops to 12.5pH. This allows you to get the same performance at the IC
via attachments with 87.5pH assigned to the mounted capacitors. Six
capacitors would get you to 83pH covering the requirement. To cover the
low frequency end increase the Farads in whatever way you prefer: One
cap a different value, or scaling some or all of the caps. Now you've
dropped the capacitor count by 40%, by reducing the cavity inductance,
not the capacitance.
Istvan has championed the benefits of thin dielectric for many years and
has numerous publications on the subject. You can also pull my
DesignCon 2009 paper explaining trade-offs from www.ipblox.com/papers.html.
Steve.
jemanakk@xxxxxxxxxxxxxxxxxxx wrote:
> Hi Lee,
> How about when embedded capacitors are used (for example: power and GND
> separated with 2 mil FR4 (~ 0.5pF/sq. inch) or C-ply (~ 5pF/sq. inch)
> capacitor between power and GND planes?
> In this case:
> 1. Mfg. recommendations for decoupling Caps (0.1/0.01 uF per power pin)
> are still valid?
> 2. Is it possible to eliminate decoupling caps for the power pins
> (especially, if C-ply is used)? Or use 50% or less decoupling capacitors
> (for example 1 cap for 5 power pins)?
>
> Common design practice for decoupling caps:
> Many vendors/application notes recommend to use 0.1uF per power pins,
> 0.01uF per power pins (in some cases 0.001uF)
> (I have seen Gbit Ethernet PHY, USB2.0-HS with design recommendation to
> use 0.1uF and 0.01uF)
> Note:
> 0.1uF or 0.01 uF decoupling caps (ceramic, in 04 size package) are
> generally used in my designs.
>
> 3. Is there any generalized best design practice
>
>
> Best regards,
> Joseph
> -------------------------------------
>
>
>
> "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
> Sent by: si-list-bounce@xxxxxxxxxxxxx
> 03/30/2010 05:01 PM
>
> To
> "Gene Glick" <gglick@xxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx"
> <si-list@xxxxxxxxxxxxx>
> cc
>
> Subject
> [SI-LIST] Re: decoupling capacitor placement/route
>
>
>
>
>
>
> Gene,
>
> There are many good books on this subject. Eric Bogatin's comes to mind.
> Istvan Novak's is another. Mind does as well!
>
> In order to design a good power delivery system, it is necessary to couple
> the power and ground planes together with a very thin insulator (2 mils is
> a good choice.) When you do this, the location of the capacitors is
> unimportant as they are all "close" to the parts they are expected to
> supply. You are correct, the right thing to do is minimize the inductance
> in series with these capacitors (their connecting structures). The best
> you can do is connect both ends of your capacitors into their respective
> planes with the lowest inductance mounting structures you can design that
> are manufacturable. Don't worry about sharing pins with the ICs.
>
> Yes, applications notes call out all sorts of bizarre methods of mounting
> capacitors. Some EMI gurus do as well! Most of them are pretty
> unreliable
> when it comes to designing your power delivery subsystem. Get one of
> these
> books and get some good advice on how to do this design task.
>
> Hope this helps.
>
> Lee Ritchey
>
>
>
>> [Original Message]
>> From: Gene Glick <gglick@xxxxxxxxxxxx>
>> To: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
>> Date: 3/30/2010 3:04:23 PM
>> Subject: [SI-LIST] decoupling capacitor placement/route
>>
>> Where is it best to place decoupling caps (surface mount)?
>>
>> 1) A trace connects an IC power pin to the cap. Then, the cap connects
>> to a trace and finally a via to power plane. (these cheezy ascii
>> drawings don't alway work, but here goes)
>>
>> |PowerPin|------| CAP |----|via|
>>
>>
>> 2) Power pin, to short trace, to via to power plane. Then either place
>> the decoupling cap top or bottom of the bard
>>
>> |PowerPin|-----|via|----|CAP|
>>
>>
>>
>> I contend that one reason for going to surface mount chips is to
>> minimize lead inductance. Option 1 seems to negate that philosophy.
>> Seems that option 2 is better in this regard. Yet, many data sheets
>> recommend option 1, thinking the chip is forced to get power from the
>> cap first, by nature of the physical layout. I'm willing to bet the
>> inductance of the via is far lower than the trace inductance of option
>>
> 1.
>
>> In your experiences, which is more correct? Or maybe another method is
>> better yet :)
>>
>> regards,
>>
>> gene
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>
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
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