[SI-LIST] decoupling capacitor placement/route
- From: Gene Glick <gglick@xxxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 30 Mar 2010 17:02:21 -0400
Where is it best to place decoupling caps (surface mount)?
1) A trace connects an IC power pin to the cap. Then, the cap connects
to a trace and finally a via to power plane. (these cheezy ascii
drawings don't alway work, but here goes)
|PowerPin|------| CAP |----|via|
2) Power pin, to short trace, to via to power plane. Then either place
the decoupling cap top or bottom of the bard
|PowerPin|-----|via|----|CAP|
I contend that one reason for going to surface mount chips is to
minimize lead inductance. Option 1 seems to negate that philosophy.
Seems that option 2 is better in this regard. Yet, many data sheets
recommend option 1, thinking the chip is forced to get power from the
cap first, by nature of the physical layout. I'm willing to bet the
inductance of the via is far lower than the trace inductance of option 1.
In your experiences, which is more correct? Or maybe another method is
better yet :)
regards,
gene
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
