[SI-LIST] Re: decoupling capacitor placement/route

Gene the idea is to minimize the inductance seen by the IC.  So to 
answer your question you need to compare the inductances involved.

In case 1. you've imposed what is likely to be a pretty big inductor 
between the IC pin and the cap.  You can estimate that inductor's value as:

L = 32pH * H * L/W

You can estimate the inductance of a via pair as:

L = H*32pH / pi * ln( 2*S/D ) 

Where H is the height of the trace in mils above a ground plane, or well 
bypassed RF plane connected to a different rail for the straight trace, 
or the distance to the center of the power cavity from the surface for 
the vias.
L and W are length units in the same dimension:  cm/cm, inch/inch, 
mils/mils, etc.
S is the center to center via spacing
D is the via DRILL diameter

For example if you have a plane 5 mils below the top surface of the PCB, 
then a 5mil wide, 25mil long trace will cost you 5 squares at 160pH / 
square or 800pH, give or take.  Fatten the trace up to 10 mils and it 
drops to 400pH and so/on

If on the other hand you have a power cavity right there then a pair of 
power / ground vias from the IC spaced one mm apart will cost you about 
100pH to get to the cavity, as will the vias from the cap.  The common 
"wisdom" is to always follow such an approach.  Good engineering 
practice says do the math and compare your options. 

Steve.
Gene Glick wrote:
> Where is it best to place decoupling caps (surface mount)?
>
> 1) A trace connects an IC power pin to the cap.  Then, the cap connects 
> to a trace and finally a via to power plane.  (these cheezy ascii 
> drawings don't alway work, but here goes)
>
>   |PowerPin|------| CAP |----|via|
>
>
> 2) Power pin, to short trace, to via to power plane.  Then either place 
> the decoupling cap top or bottom of the bard
>
>   |PowerPin|-----|via|----|CAP|
>
>
>
> I contend that one reason for going to surface mount chips is to 
> minimize lead inductance.  Option 1 seems to negate that philosophy. 
> Seems that option 2 is better in this regard.  Yet, many data sheets 
> recommend option 1, thinking the chip is forced to get power from the 
> cap first, by nature of the physical layout.  I'm willing to bet the 
> inductance of the via is far lower than the trace inductance of option 1.
>
> In your experiences, which is more correct?  Or maybe another method is 
> better yet :)
>
> regards,
>
> gene
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-- 
Steve Weir
IPBLOX, LLC 
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