[SI-LIST] Re: "checkered" copper plane question
- From: "Arjan Timmer" <Arjan.Timmer@xxxxxxxxxx>
- To: <ptaddoni@xxxxxxxxxxxxxxxxxx>, <williamm@xxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Tue, 13 May 2003 21:07:53 +0200
I do not really know the term "checkered copper plane" but if the same is
ment as "plating balance" then it indeed is for manufacturing reasons and
it has nothing to do with electrical aspects. As Paul says, it causes a
uniform
distribution of copper all over the board, to prefend it from bending.
Arjan Timmer
Consulting Engineer
Sintecs B.V.
www.sintecs.nl
----- Original Message -----
From: "Paul Taddonio" <ptaddoni@xxxxxxxxxxxxxxxxxx>
To: <williamm@xxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, May 13, 2003 8:02 PM
Subject: [SI-LIST] Re: "checkered" copper plane question
> It improves the manufacturability during wave solder operations.
> Big blank areas cause problems somehow, better that the whole board have a
> more uniform
> distribution of copper on it.
>
> -----Original Message-----
> From: Bill Mueller [mailto:williamm@xxxxxxx]
> Sent: Tuesday, May 13, 2003 1:36 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] "checkered" copper plane question
>
>
>
> Hello all,
>
> I've been hitting a couple embedded design shows lately
> and have been seeing a couple prototype boards that have
> the top and bottom copper planes 'checkered'
>
> That is instead of a large continuous plane, the plane has
> been cut into a grid of 1-2mm squares.
>
> Has anyone else seen this? What are the benifits of this
> type of layout?
>
> Thanks,
> -Bill
>
>
> BTW: The guys manning the booth had answers
> ranging from 'I don't know' to 'better aestetics' to 'complex proprietary
> EMI interfusion grid' :)
>
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