> I've been hitting a couple embedded design shows lately > and have been seeing a couple prototype boards that have > the top and bottom copper planes 'checkered' > > That is instead of a large continuous plane, the plane has > been cut into a grid of 1-2mm squares. If it's copper squares where you didn't ask for any, I think it's called "auto-thieving" and it's intended to balance the amount of copper etching across the board. Otherwise they can get uneven etching. If it was supposed to be a solid plane but was cut up into lots of little unconnected copper squares, then it sounds like a mistake. If it's a grid of square holes, leaving a mesh of continuous lines, a few things come to mind. One is (again) to balance the amount of etching. Another might be to provide a surface for something else to adhere to. I've heard of this done on layers of IC packages (to get the dielectric layers to adhere to one another, they don't adhere to metal very well). I suppose the same might happen on a circuit board? Although usually they roughen up the copper surface to help with that, I think. Or maybe the layout person didn't know how to do a solid fill so he built it using a mesh of traces. If it's supposed to be a solid plane (reference for an adjacent stripline layer), making it a grid does noticeably change the impedance. Regards, Andy ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu