[SI-LIST] Xilinx IBERT Testing
- From: Chris Johnson <cjohnson@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 15 Jul 2011 00:53:48 -0400
I am debugging a board with a Virtex-6 HX380 chip and having some issues
with getting low error rates using the Xilinx IBERT tool. I can tweak
the MGTH parameters to have zero or near-zero errors for a PRBS7
pattern, but not for longer patterns, such as PRBS15/23/31. Is there a
particular design flaw that is more likely to cause pattern sensitive
failure for longer PRBS patterns, or could it be just about anything?
The links are running at 10.3125 Gbps.
Thanks,
Chris
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