[SI-LIST] Re: Temperature Problem
- From: Ed Sayre III <esayre3@xxxxxxxx>
- To: prasadsa@xxxxxxxxxx
- Date: Tue, 28 Sep 2004 12:21:46 -0400
Prasad,
The issue is no the interconnect. The issue causing your failure is the
device. The relative percentage change of the PCB parameters with
temperature as compared to the silicon device parameters is minimal. At
high temperature the electron mobility of the silicon drops, and the gain
of the outputs follows which in turn reduces the swing of your
outputs. Also an increase in jitter is seen and will close your data
eye. This is further compounded by the increased jitter in the clock also
due to the temperature effects
I concur with Steve Wier's comments to get your timing margins at
temperatur. This will establish your timing margins and identify your root
failure mechanisms. You can then refine your design from there.
Have fun
-Ed Sayre
At 07:01 PM 9/28/2004 +0530, saprasad wrote:
>Hi All,
>Here is the details of problem we are facing:
>
>We have developed the GP7000 Main Board V1.0 which is running at 258 MHz,
>while the version 1.2 developed at production site is running at 250 MHz
>at normal temperature.
>
>Client is testing the board at 65 deg chamber temperature. At this
>temperature the board stops working because the temperature at CPU will be
>near to 70 deg. Please note that the CPU and Memory are commercial grade.
>As per client's past experience, other products are running above 70 deg
>temp at 200 MHz.
>
>Is it possible to know what will happen to the CPU-Memory interface
>running at 250MHz at 70 deg ?
>The failure is due to component operating temperature range or due to some
>synchronization loss between Memory and CPU?
>What will be the behavior (impedance, rise time, fall time effect) of
>tracks at 70 deg ?
>
>We have track length of 4 inch between CPU(S3C2410) and
>Memory(HY57V561620B). Whether this is playing any role at higher temperature?
>
>Please advise us if you have any suggestions to sort out this problem.
>
>Regards,
>Prasad
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