[SI-LIST] Re: Stimulus for spice-to-IBIS
- From: "Andrew Ingraham" <a.ingraham@xxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Dec 2006 11:35:39 -0500
> When I translate spice model to ibis model, how can I determine the edge
> rate of stimulus from core, i.e in V-T curves.
You can use SPICE and simulate your buffer including a stage or two further
back from the point where you make your IBIS I/O buffer boundary, and then
observe the waveform at the boundary.
This is no different than any other SPICE problem, is it? The fact that you
are making IBIS models is irrelevant.
> Does 1ps is really the proper value, and truly the high-speed internal
> edge
> rate?
Of course not. The "proper" edge rate is whatever it really is, whether it
is 1ps or 1ns. 1ps is kind of fast; I'd expect it to be an order of
magnitude or so slower; but it depends on technology and circuit design
in the chip.
But the real question is, does it matter? Perhaps not. If your SPICE model
includes enough buffering, the stimulus edge rate doesn't have very much
effect on how the buffer switches, assuming you don't make it TOO slow. If
so, 1ps is as good a value as any. Also keep in mind that circuit
simulators sometimes don't like abrupt changes, which can sometimes cause
the simulation to abort.
> Is it necessary that I assign different edge rate in different PVT
> condition?
Try different edge rates and see what effect it has. That should answer
your question.
Regards,
Andy
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