[SI-LIST] Stimulus for spice-to-IBIS

Hello all,
When I translate spice model to ibis model, how can I determine the edge
rate of stimulus from core, i.e in V-T curves.

A template from Cadence said: You can optionally set the edge rate for the
chip signal into the I/O cell. The default is set to 1psec, which is
representative of a typical high-speed chip's internal edge rate.


                             Vpls_r Pls_r 0 PWL 0.0ns PD_ref 1.0ps PU_ref
100ns PU_ref                                                        

                             Vpls_f Pls_f 0 PWL 0.0ns PU_ref 1.0ps PD_ref
100ns PD_ref "

Does 1ps is really the proper value, and truly the high-speed internal edge
rate?

Is it necessary that I assign different edge rate in different PVT
condition?

And does the edge rate impact on buffer delay?

Regards

Bright 

 



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