[SI-LIST] Re: Decoupling Strategy??
- From: Istvan Novak <istvan.novak@xxxxxxxxxxx>
- To: hreidmarkailen@xxxxxxxxx
- Date: Wed, 27 Dec 2006 18:55:25 -0500
Agathon,
Mark may be away from his office, so let me try to help you with
my understanding.
Power Distribution Networks can feed single loads or multiple loads.
With the independent supply rails mushrooming in our systems, we
have to try to feed as many loads (chips) from a single supply rails
as we can without compromising system performance. Some supply
rails will remain point of load, with only one consumer. For those,
we can analyze the required impedance profile, but unless we really
get into the fine details of varying current density over multiple
current paths (like paralleled pins and vias), probably the target
impedance on the board and on the package will be the same or
similar. (Note: this assumes we stop somewhere on the package.
If we continue our journey onto the silicon, the impedance target
is likely to change)
When we can combine several chips on the same supply rail, the
board side has to feed all of them in parallel, hence the target
impedance on the board becomes lower with respect to the individual
target impedances of the chips on their packages.
Hope this helps.
Best regards and HAPPY HOLIDAYS for everyone on the list.
Istvan Novak
SUN Microsystems
agathon wrote:
>Mark,
>A clarification, please.
>Your statement "The two target impedances, 1and 3, will be different ..."
>doesn't seem fully clear.
>
>Q: How so and why?
>Do you mean that the pkg target Z depends on which pwr/gnd pkg path, due to
>each path having a different current profile, and therefore all pkg
>Z-targets are different, in general, than for the pcb?
>
>Regards,
>Agathon
>
>
>On 12/15/06, Mark Alexander <mark.alexander@xxxxxxxxxx> wrote:
>
>
>>Simba,
>>
>>
>>I agree with your hunch about dT. To go one step farther, there's not
>>just one dT and one dI -- there are multiple di/dt's, since there are
>>different current demands happening on different timescales.
>>
>>
>>
>>For a designer of boards (I assume this is your case), one would hope
>>that the device vendors could be trusted to take care of the power
>>system beyond some cutoff frequency. After all, the PCB is only
>>effective up to the frequency of the inductive bottleneck a device
>>package and its via field. This allows you, as you say below, to
>>"eventually move beyond the right side of the resonance curve and" not
>>care about the fact that you "will probably violate your impedance
>>target at some frequency." That crossover area between PCB PDS and
>>device PDS is where the device will begin to take over. The PCB/system
>>designer then has two numbers of interest: the impedance target and the
>>high-frequency cutoff.
>>
>>
>>
>>For a device vendor (this is my case), the two numbers of interest are:
>>the impedance target and the low-frequency cutoff. The low-frequency
>>cutoff is first a matter of getting something low enough such that the
>>device isn't making unrealistic demands on thee PCB (to take care of
>>providing a low impedance at frequencies above the bottleneck of the
>>device package and via field, otherwise the device can't work), and
>>second a matter of how convenient/usable the vendor want to make the
>>device for system designers to use. The lower the low-frequency cutoff,
>>the easier the PCB designer's job, but the more on-package capacitance
>>is required (which adds to device expense and complexity).
>>
>>
>>
>>Together, that's four numbers: (1) PCB target impedance, (2) PCB
>>high-frequency cutoff, (3) Device package-and-die target impedance and
>>(4) device package low-frequency cutoff. The two target impedances, 1
>>and 3, will be different (the simple rule of thumb you cite in your
>>second paragraph, 50% of DC current, is a single number and obviously an
>>approximation). The PCB cutoff point is dependent on the device cutoff
>>point, as the system designer will want to extend past the package
>>cutoff have some area of overlap.
>>
>>
>>
>>Determining and communicating these numbers largely comes down to the
>>device vendor. This means making design rules based on expected device
>>activity, and package cutoff point. In the case of my company, we
>>specify these terms indirectly with guidelines on capacitor values and
>>quantities*.
>>
>>
>>
>>That leaves the question of how the device vendor determines their
>>numbers - (3) the target impedances and (4) the maximum low-frequency
>>package cutoff point. There's obviously a lot of secret sauce in this
>>area - some mixture of simulation, measurement and theory. One big
>>advantage the device vendor has is access to test structures that the
>>PCB/system designers typically don't have access to. The simplest of
>>these are exposed test points on the top surface of a package substrate
>>that allow for direct measurement of noise on the package power system
>>under device operation. More sophisticated are silicon structures
>>designed for noise measurement at the die level, and indirect noise
>>measurements through functional and timing tests (such as data window
>>sweeping or measuring clock jitter and correlating to known noise
>>levels).
>>
>>
>>
>>If you're a PCB/system design buying your silicon devices from a
>>separate vendor, you are at the mercy of the vendor - demand complete
>>power system guidelines. If you're also rolling some of your own ASICS,
>>then it's up to you to make the engineering decisions about all four
>>numbers.
>>
>>
>>
>>Regards,
>>
>>mark
>>
>>
>>
>>
>>
>>*These can be found in two places: Device User Guides and an Appnote.
>>See Virtex-5 PCB Design Guide, Virtex-4 PCB Design Guide, and XAPP623.
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>>On Behalf Of Simba Julian
>>Sent: Friday, December 15, 2006 7:23 AM
>>To: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Decoupling Strategy??
>>
>>
>>
>>Greetings to All,=20
>>
>>
>>
>>With respect to formulating a decoupling strategy. Assuming that you
>>
>>have access to frequency domain board analysis simulation tools such as
>>
>>SiWave, PowerSI or similar SPICE tools, it should be easy to look at the
>>
>>impedance profile as seen by ICs on your design based on plane shape,
>>
>>stackup, decoupling capacitor placement, power etch connecting ICs to
>>
>>planes and Decoupling caps to planes. =20
>>
>>
>>
>>So I've heard it said that you take the max dV that you can allow for
>>
>>ripple on your power rails and divide it my the dI mimicking the
>>
>>switching transients of your IC (i.e. processor switching from low
>>
>>power state to fully active). While the dI is not always known to the
>>
>>SI engineer using off the shelf parts, I've seen a presentation that
>>
>>suggests a method of taking the Max current (typically known) and
>>
>>dividing it in half and assume that as the dI, implying that my IC uses
>>
>>half the power/current in a low power state.... I can buy that. With
>>
>>this new dV and dI I can come up with an impedance target.
>>
>>
>>
>>Here's the question: =20
>>
>>
>>
>>How do you determine what max frequency is this max impedance target a
>>
>>requirement? It's a trivial exercise to verify through simulation the
>>
>>effects of adding more caps, and staying under this impedance target for
>>
>>low/mid frequencies, which may be good enough....or.... maybe I need to
>>
>>add a few more caps to keep my impedance under the target at slightly
>>
>>higher frequencies..... or worst yet... maybe I need to consider
>>
>>changing my stackup to have better use of buried capacitance between the
>>
>>planes....or .... thin core dielectrics.... or other exotic
>>
>>materials..... or..
>>
>>
>>
>>Point is, when making this analysis based on impedance target, you
>>
>>eventually move beyond the right side of the resonance curve and will
>>
>>probably violate your impedance target at some frequency. I'm quite
>>
>>sure it has something to do with the dT of the dI that we have come up
>>
>>with a rule of thumb for but I'm interested in knowing how do you
>>
>>determine this target from datasheet specs or any other practical
>>
>>means(Unless I have this all wrong :)).
>>
>>
>>
>>Simba
>>
>>EMC Corporation
>>
>>
>>
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