[SI-LIST] Staggered IO Layouts
- From: Adeel AHMAD <adeel.ahmad@xxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 25 Feb 2004 11:51:37 +0530
Hello all,
I am working on Staggered IOs for which i need information like-
* specific issues to be kept in mind while making Staggered IOs with
respect to its layout.
* effect on ESD response when using Staggered Pads as compared to In-line
Pads.
* how different is the performance of IOs(and Power pads) when placed in
inner and outer rows of staggered pads (if there is any such difference).
* other issues specific to making Staggered IO/power pads that i need to
keep in mind.
can anyone throw some light on any of these issues or let me know any
web-link/document where i can find detailed information on Staggered pads
and staggered IOs ?
thanks & regards,
Adeel Ahmad
ST Microelectronics
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