[SI-LIST] Current mode current stealing simulation by IBIS file
- From: "Sogo Hsu" <sogo.hsu@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 25 Feb 2004 08:10:47 -0000
Hi, Gurus,
A question regarding current mode current stealing circuit
simulation confused me for a long time. The simulation results
totally different from the measured as well. To understand the cause
of discrepancy, I tried to set up two kinds of circuit, one is
voltage mode and the other one is current mode. In general, IBIS
file describe the v/t curves of I/O cell with test feature. We can
easily generate the same v/t curve for these two. However, the Spice
simulation indicated the results are totally different if the whole
link is under considered. The behavior of current mode spice model
is similar with the measured. In my opinion, this phenomenon can be
analog to TE and TM mode. Therefore, the refection condition is
definitely different even they have owned same v/t curve in IBIS
file. My question is, how we overcome this issue if we only use IBIS
file for simulation. In general, we can only get IBIS files from
vendors.
Can any expert on this topic share the experience to me? Thank you
in advance.
Best regards,
Sogo Hsu, Ph. D.
Simulation center/PCEG/Foxconn Electronic
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