Hi SI Gurus, I am working on a 10 layer board, stackup is: 1 component/signal 2 ground 3 signal 4 power 5 signal 6 signal 7 power 8 signal 9 power 10 component/signal The technology is mixed, mostly 1 to 3 V logic levels plus some LVDS and a little analog. The power layers are all fairly well bypassed, across the board. There are also a number of local power planes embedded in the signal planes. The issue is, one local power net, with relatively heavy supply requirements, is currently implemented with 3 plane areas on 3 separate signal layers, stitched together with vias. I am thinking it would be better to split the power plane on layer 9 to give this supply its own dedicated plane area, as layer 9 does not deliver in that area. The concern is signals crossing the plane split, but since there are no signals on layer 10 in that area, and layer 7 is a well bypassed power plane, it shouldn't hurt to split layer 9? I know each design is unique and requires its own proper study, but if anyone would share their general impressions of this scenario, I would appreciate it! Thanks, Ivor Bowden ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu