[SI-LIST] Re: Splitting this power plane.
- From: steve weir <weirsi@xxxxxxxxxx>
- To: ivor@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Fri, 11 Mar 2005 13:59:23 -0800
Ivor, be afraid of that stack-up. Be very afraid. With only layer 2 as
ground, I expect it to be an EMC and signaling nightmare. Please see
previous thread discussions on the excellent Intel server 8 layer stack-up
and why it works so well, as well as discussions on cavity resonance.
Steve.
At 10:16 AM 3/11/2005 -0800, Ivor Bowden wrote:
>I should have mentioned, there is ground flood on all unused areas of
>all signal and component layers, to help make up for there being only
>one ground plane.
>Ivor
>
>on 3/11/2005 9:46 AM Ivor Bowden wrote:
>
> >Hi SI Gurus,
> >
> >I am working on a 10 layer board, stackup is:
> >
> >1 component/signal
> >2 ground
> >3 signal
> >4 power
> >5 signal
> >6 signal
> >7 power
> >8 signal
> >9 power
> >10 component/signal
> >
> >The technology is mixed, mostly 1 to 3 V logic levels plus some LVDS and
> >a little analog.
> >
> >The power layers are all fairly well bypassed, across the board.
> >
> >There are also a number of local power planes embedded in the signal planes.
> >
> >The issue is, one local power net, with relatively heavy supply
> >requirements, is currently implemented with 3 plane areas on 3 separate
> >signal layers, stitched together with vias. I am thinking it would be
> >better to split the power plane on layer 9 to give this supply its own
> >dedicated plane area, as layer 9 does not deliver in that area. The
> >concern is signals crossing the plane split, but since there are no
> >signals on layer 10 in that area, and layer 7 is a well bypassed power
> >plane, it shouldn't hurt to split layer 9?
> >
> >I know each design is unique and requires its own proper study, but if
> >anyone would share their general impressions of this scenario, I would
> >appreciate it!
> >
> >Thanks,
> >
> >Ivor Bowden
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