[SI-LIST] Re: Split Ground Planes

Hi Rakesh,

While it is possible for splits to work in a case such as this, one 
should not split planes or implement a feature just because is is a 
rule of thumb or "design rule." I have seen very real problems caused 
by splits under a chip  [like chip latch-up in response to noise], but 
in other cases it may be necessary.

For the latch-up example, imagine the I/O of the chip referenced to 
different grounds that have a common point some distance away on the 
board. Noise on the board can generate significant voltage in the loop 
between the sides of the chip.....bingo, latchup!

There are too many variables in a board design to make a one rule fits 
all.  One must test design assumptions regularly to make sure they 
still apply.

All signals form a loop, source to load and back again. Its the "back 
again" that tents to cause the problems. In this case, if the 
returning current is forced to go around a cut in a ground/power plane 
a loop is formed and there will likely be all sorts of problems, some 
of which may only become known after the design hits the field.

I have found that one is much closer to the final design to start from 
solid ground and split only when it is proven necessary. When problems 
arise, they are often from low frequency signals causing drop across 
resistance (hum bars if video). But if a split is made to address such 
a problem, care must be taken on the high frequency side.

Some chips have separate analog digital ground pins. When this is 
done, it may be (depending on the case, not a general rule) the chip 
designer is trying to avoid common impedance coupling through the 
parasitics of the package (usually lead inductance). If this is the 
case, a solid ground is probably best.

But, you as a designer should know why a design is done a particular 
way. If you are going to put a split in a ground plane, you should 
understand where the currents are flowing and exactly what you are 
trying to accomplish. Following a general rule is not a substitute for 
  being diligent in a design.

Often, I see posts to this list asking for advice, and usually there 
is a lot of good advice given. Keep in mind though, there are many 
many variables in a design that a simple question/description does not 
convey to the group so the advice may or may not apply. One must still 
thoroughly understand the design to know when given advice is 
applicable. There is no "free lunch" here. Engineering is work, as 
pleasurable as it is for most of us.

For your question about a split under an ADC chip there are many 
points you are leaving out:

- how long is the split?
- how are you getting paths from one side to another (if applicable)
- is the split causing ground currents to form a loop?
- have you tried a solid ground?
- what is the chip designer trying to accomplish (package parasitics 
or concern at the board level)

One thing to keep in mind: at high frequencies (tens to hundreds of 
MHz and higher), a few pF here and a few nH there couple everything 
together anyway and you may not be accomplishing what you think with a 
split.

Whew! I hope I have not caused more confusion instead of less, got 
sort of carried away.

Doug

rakesh wrote:

> Hi All,
> 
> While appreciating what Guru Doug has mentioned,
> 
> I have a doubt.  Would the Split in the Analog and Digital ground below a
> ADC qualify as a split plane
> 
> Best Regards
> 
> Rakesh
> 
> 
.......

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