[SI-LIST] Re: Simulation problems with SSTL2 IBIS model


Hi Dirk,
You have not provided any details of the SI tools used for simulation.  I
too have come across a similar issue.  I used HyperLynx simulator to
simulate a differential SSTL2 clock signal, and my waveforms were very
close to the actual waveforms I observed on an oscilloscope.  However,
another location which performed similar simulations on the same design
using XTK simulator, observed significant ringing on the waveform.  I too
would be interested to know what can cause this.

Regards, Ravinder
PCB Development and Design Department
IBM Corporation
Email: ajmani@xxxxxxxxxx
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                      Linnenbruegger Dirk                                       
                                     
                      <Dirk.Linnenbruegger@fujitsu-s        To:       
"'si-list@xxxxxxxxxxxxx'"                      
                      iemens.com>                            
<si-list@xxxxxxxxxxxxx>                                 
                      Sent by:                              cc:                 
                                     
                      si-list-bounce@xxxxxxxxxxxxx          Subject:  [SI-LIST] 
Simulation problems with SSTL2 IBIS  
                                                             model              
                                     
                                                                                
                                     
                      09/19/2002 04:37 AM                                       
                                     
                      Please respond to                                         
                                     
                      Dirk.Linnenbruegger                                       
                                     
                                                                                
                                     
                                                                                
                                     





Hi SI-List members,

I have performed some simulations using an IBIS
model of a differential clock buffer and I wonder
about the strange waveform behavior.
The simulations have been computed with two very
common simulation tools.

The output signals cross near the low voltage state
instead of in the middle of the high and low state.
Furthermore high ringing occurs although the
transmission lines are terminated properly.

After some investigations of the IBIS file I found
out, that the simulation results look much better,
if the [ramp] data will be used instead using the
[rising/falling waveforms].

But, of course these simulation results based on the
ramp data don't correlate very well to the reference
waveforms, which are based on an Hspice transistor
level model. Therefore I tried to get some more
simulation results which have been computed with some
other tools. I was really surprised, that the new
results of the other tools look quite well.

From my point of view it seems, that the IBIS file is
OK and that there might be some problems in our tools
to handle this kind of IBIS file.

So, I would like to know if someone of you had similar
problems or an idea how to solve this problems.


Thanks
Dirk Linnenbruegger
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