[SI-LIST] Silicon Valley Chapter - Speaker: Lee Ritchey
- From: Bob McCreight <bobmccr8@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 9 May 2003 07:59:50 -0700 (PDT)
Sorry about the late notice but space has just been
made available for more people and you _MUST_ RSVP by
noon Monday... send to SV_IPC@xxxxxxxxx
The Silicon Valley Chapter of the IPC Designers
Council is excited to announce that their next meeting
will be Tuesday, May 13 at Cadence Design Systems in
San
Jose. 11:30AM to 1:30PM; $1 for members, $5 for
visitors (please bring a business card for check-in).
Lunch is provided by our sponsor: Cadence Design
Systems
RSVP is required, send to SV_IPC@xxxxxxxxx
The Topic:
Calculating Impedance and designing cross sections
Presenter: Lee Ritchey
LEE RITCHEY, BSEE, is owner of Speeding Edge, a
consulting firm specializing in high-speed design
consulting and training.
Lee Ritchey is currently working with major suppliers
of gigabit and beyond internet products as well as a
variety of wireless products. He has 30+ years
experience in the packaging of high performance
equipment from microwave satellites to supercomputers.
Until recently, Lee was Director of Packaging
Engineering at 3Com Corporation, a major network
equipment supplier. Lee is currently working full time
as a consultant to several major manufacturers of
Gigabit and higher Ethernet products.
[In December 1998, EE Times profiled Lee Ritchey in
its People 98 section, characterizing him as
"high-speed design's ratchet man," and stating that
"anyone who wants to learn the ins and outs of
high-speed board design can't do much better than to
turn to Lee Ritchey..." Lee was one of 19 technical
gurus recognized by EE Times as major drivers and
innovators in their fields, specifically CAD/CAE tools
for simulation and design of PCBs.]*
He is on the editorial review board for Printed
Circuit Design Magazine and is a regular contributor
of design articles to a variety of publications. He
has taught his High Speed Design course to more than
3000 engineers and designers in several countries. He
is a regular lecturer at the Printed Circuit Design
Conference, the IPC conferences and at UC Berkeley
Engineering Extension.
- - - - - - - - - -
Location:
Cadence Design Systems
2655 Seely Ave., Bldg 5 (Pebble Beach Room)
San Jose, CA
May 13 Tuesday
Time: 11:30AM to 1:30PM
$1 for members, $5 for visitors
(please bring a business card for check-in).
Lunch is provided by our sponsor:
Cadence Design Systems
RSVP Required, send to SV_IPC@xxxxxxxxx
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