[SI-LIST] Re: Signal Routing in outer layer
- From: "Sol Tatlow" <Sol.Tatlow@xxxxxxxxxxxxxxx>
- To: <bijesh.t@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 20 Oct 2004 11:31:18 +0200
Hi Bijesh,
one important point not yet mentioned, is that tracks on external layers
(which are then plated up) vary in thickness, depending upon the routing
density in the local area (less tracks around the diff. pairs means more
copper). This makes the impedance harder to control precisely, due to
varying cross-section of tracks across the board.
'Thieving' pads can be applied to fill open areas (the PCB manufacturer
will often ask if he can do this anyway, as it also means less copper to
be removed in the etching process), but the problem exists nevertheless,
even if you are ok with allowing this.
To be on the safe side, you should confirm with your manufacturer what
kind of influence on the tolerance range of controlled impedances it
would have - for example, +/- 5% might be possible, but perhaps only on
inner layers.
For this reason, it is PREFERABLE to route critical sigs on inner =
layers.
Incidentally, on boards with multiple microvia layers (2-x-2 and above),
tracks on some of the INNER layers may also be affected by the plating
process - laser microvias have to be plated, of course - although with
some processes, in some cases, such as the Neo-Manhatten (Bump) process,
even the outer layers are not effected (with a pure SMT board).
Mit freundlichen Gr=FC=DFen
____________________________________
Sol Tatlow, M.Eng. (Oxon)
ProDesign Electronic & CAD Layout GmbH
Product Developer
Albert-Mayer-Str. 16
D-83052 Bruckmuehl
Phone: +49 (0) 8062-808-302
Fax: +49 (0) 8062-808-333
Mailto:sol.tatlow@xxxxxxxxxxxxxxxxxxxx
www.prodesign-europe.com
____________________________________=20
-----Urspr=FCngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
Im Auftrag von bijesh.t.b
Gesendet: Dienstag, 19. Oktober 2004 12:30
An: si-list@xxxxxxxxxxxxx
Betreff: [SI-LIST] Signal Routing in outer layer
Hi all,
I would like to get some clarification reg. the high speed differential =
signal routing in multilayer board.
1).Can we route high speed differential signal in outer layer?.
2).If we can route the differential signal in outer layer then, how do =
we
calculate the impedence.
3).What is the minimum tolereance which we can give for the outer layer
impedece.
4).If the high speed differential signal can be routed in the outer =
layer
then,how do we control the EMI issues?.
If anyone of you can help me on this,Please..
Thank you
Bijesh
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