[SI-LIST] Re: SSTl2 SSO simulation set-up
- From: Jory McKinley <jory_mckinley@xxxxxxxxx>
- To: starsilic@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 2 May 2007 10:41:35 -0700 (PDT)
Hello Canes,
You are missing the power/ground package connections from the DRIVER to the
LOAD. You can add t-line to represent your board however you when then need to
include the power/ground model for the board as well. You may have to extract
the power/ground structure of the package and board through either 3-D
simulations or careful use of formula based approximations if not provided.
-Jory
----- Original Message ----
From: Canes Venatici <starsilic@xxxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Sent: Wednesday, May 2, 2007 4:40:49 AM
Subject: [SI-LIST] SSTl2 SSO simulation set-up
Hi,
I could see in some documents, the SSO simulation set up for SSTL2 interface is
like below.
I want to know whether the schematic below represents the correct simulation
set-up for SSTL2 quite node
SSO simulation.
I tried inserting transmission line between Rser and Cload-Rt junction. But I
get very different values
of noise compared to the results of provided in the doc, using the below set-up.
Could anyone explain which is correct method and how the schematic below can
represent the
T.Line effectd.
VTT
____
|
|
/
\ Rt
/
\
------------ ---------- |
| | | | Rser
|
| Driver |-------| Pkg | ------------/\/\/\/\/\/\----------|
| | | model
| |
| | | |
|
------------ ------------ |
==== Cload
|
|
|
_____
__
-
Regards
Canes
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