[SI-LIST] SSO Analysis
- From: rajat.chauhan@xxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 14 Mar 2002 21:40:08 +0530
! Greetings,
!
! I would like to know if there are any guidelines and/or rules for
! conducting the SSO analysis
If by SSO (simultaneously switching outputs) analysis you mean
ground/power bounce analysis then:
First decied the number of output buffers for which a I/O supply
pair(ground and power) is assigned. Suppose you get one supply pair for
every 6 output buffers, switch 5 adjacent buffers simultaneously and hold
the 6th at logic low for ground bounce and high for power bounce
analysis.
Perform analysis on CORNER most group of buffers.
!, more than that, if there are any hints to:
! 1. How to read the results.
Check the output of your static (6th) output buffer. When kept at logic
low, its output will follow the chip-ground and therefore bounces on it
at the time of simultaneously switching.
! 2. What is a pass/fail criteria.
Knowing the max. input logic low 'Vil max' and min.input logic high
'Vih min' of the receiver which your output buffer will be driving, you
can decide your pass/fail criteria. Rough and safe criteria is, if ground
bounce exceeds 'Vil max' and power bounce goes below 'Vih min' specs of
your receiver, means fail.
But bounce over 'Vil max' may not always able to switch the
receiver. It depends on both amount and duration of ground bounce pulse
above 'Vil max'. You can say it depends on the area of pulse above 'Vil
max'. So you can allow the ground bounce to go bit above the 'Vil max' if
it is of very short duration, but how much you have to decide your self,
depending upon the reponse time of your receiver.
!
! We are using HSPICE, and the package's model given by the vendor.
!
! Any information, or experiance is welcome.
!
! Regards
!
! SS
!
!
!
! ------------------------------------------------------------------
____________________________________________
RAJAT CHAUHAN
STMicroelectronics
NOIDA
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