[SI-LIST] Re: SDRAM data issues
- From: "Mangipudi, Prasad" <Prasad_Mangipudi@xxxxxxxxxxx>
- To: "'sankar.karuppannan@xxxxxxxxx'" <sankar.karuppannan@xxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Thu, 15 May 2003 15:43:04 -0700
Sankar,
Lot of information is needed to analyze and isolate the problem. You have to
analyze - Routing of the clock and address lines (goes to multiple
SDRAMs)and their trace lengths, trace lengths of data lines relative to
clock for particular SDRAMs, data corruption in one SDRAM or many SDRAMs,
any feedback clock and how its length is matched to the clock (particularly
if clock length is different to different SDRAMs), ASIC set-up/hold time
versus SDRAM set-up/hold times, speed grades of SDRAM devices used vs. cas
latencies, Write or read data corruption versus both(can be challenging to
isolate), few address locations or many locations,.. etc before coming to
conclusions.
1. If the ASIC is a proven ASIC, verification of the board layout may hold
key. Check the routing of clock in relation to Data lines. Are the data
errors occurring in the SDRAMs where the clock trace length is much longer
than the data lines of those SDRAMs. I assume data lines are probably point
to point from ASIC to SDRAM and the clock runs to multiple SDRAMs. Extra
clock length will reduce the hold time(by the amount of additional
propagation delay) and you may see the problem because of that.
2. You can also try using a higher speed grade for the SDRAMs and see if it
works as timing margins required will be lower
3. If the clock line can be broken, you can connect a Programmable PLL clock
skew generator(from IDT or Pericom ..), connecting the clock from ASIC to
PLL as reference and using the clock output of the PLL to SDRAMs. This way
you can program the skew positively or negatively (few hundred ps to few ns
either way, programmable)and see how much margin is required and on what
side.
Hope this helps in getting started. You can send me an off line email if
you want.
Prasad
-----Original Message-----
From: Sankar karuppannan [mailto:sankar.karuppannan@xxxxxxxxx]
Sent: Thursday, May 15, 2003 5:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM data issues
Hi,
I am facing some problem in the SDRAM data lines. The problems are
whenever I am running more then 115MHz SDRAM read and write test is
failing. I connected logic analyzer to probe the signal then tests are
passing. In PCB SDRAM is placed very close to the ASIC. I do not know
the problem is due to the capacitance or ground. I gave sufficient
ground plane under the device.
If any one knows the solution please help me.
Thanks,
Sankar.K
Wipro Technologies,
72, Electronics City, Hosur Main Road,
Bangalore-561229.
Ph:+91-80-8520408 Extn: 4012/4031.
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