[SI-LIST] Re: Rise/Fall time Vs Bit rate.
- From: Yagya Dutt Mishra <ygdutt86.2@xxxxxxxxx>
- To: WinstonRaj.ST@xxxxxxxxxx
- Date: Tue, 28 Aug 2012 14:23:11 +0530
Hello Rajneesh
As far as i have understood your question, lets assume we have two case
Case A : In which 10 bits are transferred in a time window of 10 ps(i.e 1
bit per ps)
and
Case B : 2 bits in the same window i.e 10 ps simply means that the first
case is a high bit rate signal and the second case is low bit rate signal.
At the pad the capacitance will get charged and discharged producing the
corresponding data pattern which is sent from the core side.
In case of high bit rate signal , the capacitance will get very small time
window to charge and discharge.
(it may be possible that capacitance's charging time is 1.2 ps and in case
A we have one bit per ps so capacitance will be charged up to around 40%of
(logic 1 voltage) which may not cross the Vih and leads to false detection
of logic at receiver end whereas on the other hand for the case B you will
get the true detection of logic without any error because capacitance will
produce the same data pattern since it has sufficient time to get charge up
to 90%-100% of logic 1 voltage )
That is the problem of Signal Integrity (simply termed as Inter-symbolic
Interference) which is major concern in High Bit rate communication.
Yes of-course low bit rate also face the SI problem but the probability of
ISI is high in High bit rate signals.
On Tue, Aug 28, 2012 at 12:51 PM, Winston Raj S T
<WinstonRaj.ST@xxxxxxxxxx>wrote:
> Hi,
>
> Setup and hold time violations are increasing as the speed of the
> signals become faster. A clocked device requires the data to be stable at
> its input for a specified time before the first edge of clock arrives and
> called as setup time and also the input data should remain valid for a
> specified time after the second edge of the clock called the hold time.
> Violating setup and/or hold requirements can cause unpredictable output.
> Setup and hold times are decreasing as device speed increase likewise,
> there are many.
>
> Regards,
> Winston
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of rajneesh shukla
> Sent: Tuesday, August 28, 2012 12:29 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Rise/Fall time Vs Bit rate.
>
> Experts,
> We all have read that in high speed design it's rise time that creates
> signal integrity issue. By this theory, all low bit rate signals that is
> driven by fast I/O driver will also have signal integrity issues then why
> most of the time high bit rate signals are analysed for signal integrity
> issue ??
>
> Please explain what is the role of bit rate in signal integrity ??
>
> Rajneesh
>
>
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Thanks and Regards
--
*Yagya Dutt Mishra*
*STMicroelectronics Pvt. Ltd. India*
*yagya.mishra@xxxxxx*
*Mo. No :+91 8882016638*
*
*
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