[SI-LIST] Re: Rise/Fall time Vs Bit rate.
- From: Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
- To: rajneeshs123@xxxxxxxxx
- Date: Wed, 29 Aug 2012 10:38:42 -0400
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Guys;
Has any one were able to find the "pdf" of the paper in web? I did sear=
ch
and I can only find the
Designcon 2009 listing of papers presented not the contents of paper. I=
f
anyone has found it
and can share it will be of great help. Thanks in advance.
Regards;
Don Pakbaz
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|08/29/2012 10:27 AM =
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|[SI-LIST] Re: Rise/Fall time Vs Bit rate. =
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Thanks Steve, Rohit & everyone for clearing my doubt.
So if I understood it right, if low bit rate signal is data signal then=
chances of SI problem will be minimal but if it's strobe or reset signa=
l
then we must analyse it for SI problem.
As a follow-up question...I would like to know how to handle SI problem=
in
low bit rate signals like strobe or reset signal. do we need to take s=
ome
special precaution or just need to have controlled impedance & resistiv=
e
termination ? I don't think that I have ever seen resistive termination=
in
reset/strobe signal.
rajneesh
On Wed, Aug 29, 2012 at 7:00 PM, Faraydon Pakbaz <pakbazf@xxxxxxxxxx>
wrote:
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>
> Hi Istvan, Tesla;
>
> If I am not mistaken this is the paper than Istvan had in mind. It wa=
s
> presented in designcon 2009.
>
> "Switching Voltage Regulator Noise Coupling Analysis for Printed Circ=
ui=3D
> t
> Board Systems"
> Amy Luoh, Gene Garrison, Jon Powell
>
> Regards;
>
> Don Pakbaz
>
>
>
>
> |------------>
> | From: |
> |------------>
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> |Tesla <emcesd@xxxxxxx> =
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> =
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> |
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> |"Istvan Novak" <istvan.novak@xxxxxxxxxxx> =
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> =
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> |
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> | Cc: |
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> |weirsi@xxxxxxxxxx, si-list@xxxxxxxxxxxxx =
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> =
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> |
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> |08/29/2012 02:43 AM =
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> =
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> |[SI-LIST] Re: Rise/Fall time Vs Bit rate. =
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>
> Hi, Istvan
>
> Thanks a lot.
> it is a long time that there is no update on your website......
>
> Regards.
>
> Tesla.
>
>
>
>
> At 2012-08-28 19:12:18,"Istvan Novak" <istvan.novak@xxxxxxxxxxx> wrot=
e:=3D
>
> >Tesla,
> >
> >This Intel paper was at DesignCon 2009, titled
> >"Switching Voltage Regulator Noise Coupling Analysis for
> >Printed Circuit Board Systems" by Amy Luoh, Gene Garrison and Jon Po=
we=3D
> ll.
> >
> >BTW low-speed buses often fail because people focus on the most
> >challenging, highest-speed interconnects and then time runs out in t=
he=3D
>
> >design schedule.
> >
> >Best regards,
> >
> >Istvan Novak
> >Oracle
> >
> >
> >On 8/28/2012 6:00 AM, Tesla wrote:
> >> Hi, Steve
> >>
> >> Thanks a lot
> >>
> >> Would you give a link about the intel paper you mentioned? Be inte=
re=3D
> sted
> to read it.
> >>
> >> Regards.
> >>
> >> Tesla
> >>
> >>
> >>
> >>
> >> At 2012-08-28 16:15:37,"steve weir" <weirsi@xxxxxxxxxx> wrote:
> >>> If one is dealing with data signals, then as long as they settle =
ou=3D
> t at
> >>> valid logic levels by the time they are sampled, and remain stabl=
e =3D
> long
> >>> enough to satisfy hold time requirements, then all is good. That=
> >>> observation has lulled many a digital engineer into "Sauron's Hap=
py=3D
>
> >>> Fun-Time Intermittent Failure Party at Mount Doom"(tm) when they
> neglect
> >>> the fact that not all low-rate signals are data. Some low-rate s=
ig=3D
> nals
> >>> are timing strobes, such as TCLK on a JTAG bus. Timing strobes n=
ot=3D
>
> only
> >>> have to settle-out at valid levels, they need to be free of wavef=
or=3D
> m
> >>> artifacts like double transitions.
> >>>
> >>> Then there are high impedance dinosaur busses that say: "Hey sai=
lo=3D
> r:
> >>> For $20 dollars I'll take your induced noise around the world." =
A =3D
> few
> >>> years ago Intel presented a DesignCon paper where they described
> >>> spending the better part of a million dollars on manpower and
> >>> sophisticated software tools, as well as nearly half a year track=
in=3D
> g
> >>> down signal integrity problems on a lowly I2C bus. Every month o=
r =3D
> two
> >>> induced noise would cause servers to reset.
> >>>
> >>> Steve.
> >>>
> >>>
> >>> On 8/28/2012 12:23 AM, Rohit MISHRA wrote:
> >>>> Rajneesh,
> >>>>
> >>>> That's a good question, indeed !!
> >>>>
> >>>> You rightly pointed out that slow repetition pulses driven by fa=
st=3D
>
> driver can also have reflections & other transmission line effects bu=
t =3D
> you
> should also understand that these effects create signal integrity pro=
bl=3D
> ems
> most when they have less time to settle.
> >>>>
> >>>> The signal pulse width and duty cycle are not factors in decidin=
g
> transmission line behavior such as reflections but when you use high =
pu=3D
> lse
> width i.e. low bit rate signal, you are also giving more time to sett=
le=3D
>
> these effects before sampling at receiver end and remember, what the =
si=3D
> gnal
> looks like at sampling that matters most !
> >>>>
> >>>> Hope that helps.
> >>>>
> >>>>
> >>>> Rohit Mishra
> >>>>
> >>>>
> >>>>
> >>>> -----Original Message-----
> >>>> From: si-list-bounce@xxxxxxxxxxxxx [
> mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of rajneesh shukla
> >>>> Sent: Tuesday, August 28, 2012 12:29 PM
> >>>> To: si-list@xxxxxxxxxxxxx
> >>>> Subject: [SI-LIST] Rise/Fall time Vs Bit rate.
> >>>>
> >>>> Experts,
> >>>> We all have read that in high speed design it's rise time that c=
re=3D
> ates
> >>>> signal integrity issue. By this theory, all low bit rate signals=
t=3D
> hat
> >>>> is driven by fast I/O driver will also have signal integrity iss=
ue=3D
> s
> then
> >>>> why most of the time high bit rate signals are analysed for sign=
al=3D
>
> >>>> integrity issue ??
> >>>>
> >>>> Please explain what is the role of bit rate in signal integrity =
??=3D
>
> >>>>
> >>>> Rajneesh
> >>>>
> >>>>
> >>>> ----------------------------------------------------------------=
--=3D
>
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> >>>>
> >>>
> >>> --
> >>> Steve Weir
> >>> IPBLOX, LLC
> >>> 150 N. Center St. #211
> >>> Reno, NV 89501
> >>> www.ipblox.com
> >>>
> >>> (775) 299-4236 Business
> >>> (866) 675-4630 Toll-free
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