[SI-LIST] Return path for stripline between two power planes
- From: "geor_dai" <ma.kidman@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 17 Apr 2006 08:51:55 -0000
Dear All SI experts,
One question regarding to return path for signals and signal quality
concerns.
If we have stripline configuration as below, a signal trace S1 between
two power planes. Because limited routing space in the board, not all
high speed signals can be on S2 layer, which is better for signal
quality. So some of 2.125Gbps signals running on S1.
--------VCC1
--------S1 [2.125G PECL]
--------VCC2
--------S2 [2.125G PECL]
--------GND
My question is,
When the signal S1 is transient from high to low or low to high, which
plane would be the return path, VCC or GND? EMC/EMI impact? Any
compensation suggestion?
How much risk if we go to PCB fabrication like this stack up?
Thanks very much!
Best Regards,
George
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