[SI-LIST] Re: Return currents
- From: Jai Shanker <jswarrier@xxxxxxxxx>
- To: venki.pras@xxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 6 Nov 2007 22:06:10 -0800 (PST)
Pras,
You are getting very good technical asnwers to this
question. At a less advanced level, I have had the
same query and found this to help:
visualization of a localized, transient dip in the Vdd
plane at the driver as it pulls power for its swing.
Once you accept this, it becomes very easy to account
for current flows from elsewhere in the Vdd plane (I
think of a small L+R series combo to have this dip
hold across) to this localized dip and instantaneous
KCL /KVL equations to hold- without any particular
reference to a GND plane while the transition is in
effect.
The job of decoupling is to minimize such dips. I
would think that they ferry in enough from GND
eventually to make overall charge consistent, but they
dont (cant) react at switching speeds. That is my idea
of how the overall balance holds. This would be
'return' current in a sense.
regards,
Jai
--- Pras venki <venki.pras@xxxxxxxxx> wrote:
> Hello Guys,
> I have this confusion regarding "*Return currents*"-
>
> 1) In the paper "SSN & power plane bounce in CMOS
> technology" by Larry Smith
> (
>
http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf
>
<http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf+>).
> This is
> available online for free, so i m pasting it here.
> (I hope i can)
>
> In the following excerpt-
>
> "Suppose the transition is from low to high and the
> cross-section of the
> package has the transmission line located above a
> Vdd plane as shown in
> figure 1.The driver connects the Vdd plane to the
> transmission line through
> a low impedance.Current flows from the Vdd plane
> onto the transmission line
> which is low, say ground potential.As the wave front
> propagates down the
> transmission line, charge flows into the capacitance
> between the trace and
> the Vdd plane, raising the potential on the trace up
> to Vdd. The current
> path is complete because charge from the Vdd plane
> flows in a complete loop
> from the Vdd plane, through the driver and onto the
> transmission line that
> is referenced to the Vdd plane. If there is a ground
> plane underneath the
> Vdd plane, it is not disturbed because it is not
> part of the current loop."
>
> Where does the return current flow? Does the return
> current flow through the
> inter-plane capacitance? Doesn't it need to flow
> thru a reference plane?
>
> If it can't flow thru the Gnd plane, is it possible
> for it to flow thru the
> same power plane which is supplying the current (i
> hope not coz it will
> totally screw my fundamentals on current flow).
>
> 2)What if the package does not have an explicit
> power or ground plane
> i.e. Power
> & Gnd are normal, thin traces (like other signal
> traces), distributed
> sporadically along with other I/Os, signal, clock
> traces etc. (Although the
> power & ground traces are de-coupled inside the chip
> & if the I/O traces r
> driven using a CMOS buffer)
>
> How is the return current going to flow now, when
> the I/O traces r driven
> using the buffer?
>
> Will the return current still look to flow through
> the nearest Power or Gnd
> reference trace it finds, given they are randomly
> routed in the package like
> ordinary traces?
>
> I'd really appreciate if somebody can clear this
> nagging doubt.
>
> Thanx in advance.
>
> Regards,
> pras
>
>
>
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