[SI-LIST] Re: Return currents

Pras, in that example the Vdd plane is the signal image plane.  Once a 
signal launches into a nice continuous impedance transmission structure, 
it merrily propagates along without concern for much of anything other 
than the material properties and physical composition of the structure.

Steve
Pras venki wrote:
> Hello Guys,
> I have this confusion regarding "*Return currents*"-
>
> 1) In the paper "SSN & power plane bounce in CMOS technology" by Larry Smith
> ( http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf
> <http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf+>).  This is
> available online for free, so i m pasting it here. (I hope i can)
>
> In the following excerpt-
>
> "Suppose the transition is from low to high and the cross-section of the
> package has the transmission line located above a Vdd plane as shown in
> figure 1.The driver connects the Vdd plane to the transmission line through
> a low impedance.Current flows from the Vdd plane onto the transmission line
> which is low, say ground potential.As the wave front propagates down the
> transmission line, charge flows into the capacitance between the trace and
> the Vdd plane, raising the potential on the trace up to Vdd. The current
> path is complete because charge from the Vdd plane flows in a complete loop
> from the Vdd plane, through the driver and onto the transmission line that
> is referenced to the Vdd plane. If there is a ground plane underneath the
> Vdd plane, it is not disturbed because it is not part of the current loop."
>
> Where does the return current flow? Does the return current flow through the
> inter-plane capacitance? Doesn't it need to flow thru a reference plane?
>
> If it can't flow thru the Gnd plane, is it possible for it to flow thru the
> same power plane which is supplying the current (i hope not coz it will
> totally screw my fundamentals on current flow).
>
>  2)What if the package does not have an explicit power or ground plane
> i.e. Power
> & Gnd are normal, thin traces (like other signal traces), distributed
> sporadically along with other I/Os, signal, clock traces etc. (Although the
> power & ground traces are de-coupled inside the chip & if the I/O traces r
> driven using a CMOS buffer)
>
> How is the return current going to flow now, when the I/O traces r driven
> using the buffer?
>
> Will the return current still look to flow through the nearest Power or Gnd
> reference trace it finds, given they are randomly routed in the package like
> ordinary traces?
>
> I'd really appreciate if somebody can clear this nagging doubt.
>
> Thanx in advance.
>
> Regards,
> pras
>
>
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