[SI-LIST] Re: Return currents

Pras (and others interested in this thread)- Thanks for taking a look at
my paper from the 1999 IEEE EPEP conference.  The paper discusses a test
board that was designed to specifically address the issues and questions
brought up in your email.  It was meant to demonstrate that all of the
return current for the net on this particular PCB stackup is on the Vcc
plane.  It was also intended to show the power plane bounce expected if
return current is forced to jump from the Vcc plane to the ground plane
as demonstrated when the drivers switch from high to low.

In a planer substrate (i.e. PCB or package), most of the return current
for a trace will be on the nearest reference plane no matter what
voltage potential it happens to have (Vcc or Gnd).  This is especially
true for a microstrip over a Vcc plane as demonstrated in this example.
All you have to look at is the cross section for the PCB to determine
where the return current is.  It has nothing to do with the driver or
how it is mounted on the PCB.

On the other hand, it is obvious where the return current is right at
the driver.  If the driver switches from low to high, current must have
come from Vcc to pull up the net (assuming there is no parallel
termination resistor).  If the driver switches from high to low, current
must have come in from the net and gone into ground on the die. =20

With this particular set up, there is no problem in getting the return
current on the Vcc plane of the PCB hooked up to the Vcc of the driver
for the low to high transition, because it is a direct connection.  The
issue at hand is, "how does the return current get from the ground
terminal of the driver to the Vcc plane of the PCB when the driver
switches from high to low?" =20

There is no direct connection.  The current must pass through a
capacitance as displacement current.  This experiment was designed with
very little capacitance either inside the driver silicon, the package or
the PCB, in order to demonstrate what happens when you don't have very
much capacitance for the return current.  When current is forced to go
through a small amount of decoupling capacitance, the voltage on the
terminals of the capacitance bounces according to V =3D integral I*dt.
This is evident in the waveforms shown in the paper.  Displacement
current must flow through capacitance on the high to low transition but
not for the low to high transition.  This is the source of PCB power
plane bounce when insufficient capacitance is provided between the power
and ground planes. =20

If there are no planes in the package but only power and ground traces
near the signal, then return current for the signal will flow on those
traces (as well as other nearby signal traces).  This is the typical
situation on wire bond and lead frame packages.  A combination of
inductive coupling properties as well as the impedance on the silicon
and PCB side of the package will determine how the return currents flow.
This is very closely related to the SSN (simultaneous switch noise)
problem.

Regards,
Larry Smith
Altera Corporation

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Pras venki
Sent: Sunday, November 04, 2007 6:44 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Return currents

Hello Guys,
I have this confusion regarding "*Return currents*"-

1) In the paper "SSN & power plane bounce in CMOS technology" by Larry
Smith
( http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf
<http://www.csee.umbc.edu/vlsi/reports/ssn_pwr_planes.pdf+>).  This is
available online for free, so i m pasting it here. (I hope i can)

In the following excerpt-

"Suppose the transition is from low to high and the cross-section of the
package has the transmission line located above a Vdd plane as shown in
figure 1.The driver connects the Vdd plane to the transmission line
through
a low impedance.Current flows from the Vdd plane onto the transmission
line
which is low, say ground potential.As the wave front propagates down the
transmission line, charge flows into the capacitance between the trace
and
the Vdd plane, raising the potential on the trace up to Vdd. The current
path is complete because charge from the Vdd plane flows in a complete
loop
from the Vdd plane, through the driver and onto the transmission line
that
is referenced to the Vdd plane. If there is a ground plane underneath
the
Vdd plane, it is not disturbed because it is not part of the current
loop."

Where does the return current flow? Does the return current flow through
the
inter-plane capacitance? Doesn't it need to flow thru a reference plane?

If it can't flow thru the Gnd plane, is it possible for it to flow thru
the
same power plane which is supplying the current (i hope not coz it will
totally screw my fundamentals on current flow).

 2)What if the package does not have an explicit power or ground plane
i.e. Power
& Gnd are normal, thin traces (like other signal traces), distributed
sporadically along with other I/Os, signal, clock traces etc. (Although
the
power & ground traces are de-coupled inside the chip & if the I/O traces
r
driven using a CMOS buffer)

How is the return current going to flow now, when the I/O traces r
driven
using the buffer?

Will the return current still look to flow through the nearest Power or
Gnd
reference trace it finds, given they are randomly routed in the package
like
ordinary traces?

I'd really appreciate if somebody can clear this nagging doubt.

Thanx in advance.

Regards,
pras


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