Hello Cat: You raise a good question. The order of LRC for a discrete section within an EBD (or package model) is not properly documented. However, the IBIS committee intended to keep the same ordering convention as for the original single stage package model composed of discrete Lpkg, Rpkg and Cpkg elements. For single stage package models, the series element(s) are positioned next to the die capacitance: C_comp, and the elements are ordered to work outward to the pin interface. Multiple section package models "... start at the connection to the die ...". Each secton must follow the same LRC ordering convention as the single package model section (for consistency and in case only one section is needed). The EBD syntax is similar and follows the same ordering convention since nothing contrary is stated. Your second example provides the correct order interpretation. The series element L starts at Node A and the stage ends at Node B: > Node A > Len=0 L=2 C=1 / > Node B > B <-------|------------@@@@@------------>A > | L > | > | > =====C > | > --- Sometimes EBDs are used in place of package models. However, directly encoding a discrete package model stage as an EBD stage formats it in the incorrect order because EBDs typically start with the external pin and work inward. For example, if Pin 1 is the external pin, and Node U25.1 is the die pin 1, the syntax below attaches the C in parallel with the die node pin 1 and in parallel with C_comp. Not correct: Pin 1 Len=0 L=2 C=1 / Node U25.1 The correct representation of a single section discrete IBIS package model takes two sections in an EBD: Pin 1 Len=0 C=1 / Len=0 L=2 / Node U25.1 As previously mentioned, some EDA tools may look at time constants, and just treat small time-constant, discrete elements as distributed (or possibly recast them internally into symmetrical elements) - thereby avoiding the ordering issue. In response to your second question, the capacitance is connected to a global ground. Bob cat wrote: > Oh, I am really eager to know the answer.And if you are not sure,I still > hope you can communicate with me.If there is something wrong totally,please > let me know. > > resend the message: > > I think the description of [path description]section of the ebd file is > not detailed enough.I got confused when I meet such condition: > Node A > Len=0 L=2 C=1 > Node B > > Should I represent it like this: > > > B <---@@@@@----------|--------------->A > L=1 | > | > === C=1 > | > --- > or like this: > > > B <-------|------------@@@@@------------>A > | L > | > | > =====C > | > --- > By the way,should the capacitor be connected to ground or power? How to > determine this ? > In fact , I found many cases like the above one in the DIMM ebd file supplied > by molex. > Maybe both representation is just the same? Or there is some description I > did not noticed?Or this is really a oversight? > any response will be appreciated. > cat > cat_carl@xxxxxxxxx > 2003-09-19 > > With best regards -- Bob Ross Teraspeed Consulting Group LLC Teraspeed Consulting Group LLC 2926 SE Yamhill St. Device Modeling Division Portland, OR 97214 13610 SW Harness Lane 503-239-5536 Beaverton, OR 97008 http://www.teraspeed.com 503-430-1065 bob@xxxxxxxxxxxxx 503-246-8048 Direct ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu